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/*
* Copyright 2010-2011 Calxeda, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/circ_buf.h>
#include <linux/interrupt.h>
#include <linux/etherdevice.h>
#include <linux/platform_device.h>
#include <linux/skbuff.h>
#include <linux/ethtool.h>
#include <linux/if.h>
#include <linux/crc32.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
/* XGMAC Register definitions */
#define XGMAC_CONTROL 0x00000000 /* MAC Configuration */
#define XGMAC_FRAME_FILTER 0x00000004 /* MAC Frame Filter */
#define XGMAC_FLOW_CTRL 0x00000018 /* MAC Flow Control */
#define XGMAC_VLAN_TAG 0x0000001C /* VLAN Tags */
#define XGMAC_VERSION 0x00000020 /* Version */
#define XGMAC_VLAN_INCL 0x00000024 /* VLAN tag for tx frames */
#define XGMAC_LPI_CTRL 0x00000028 /* LPI Control and Status */
#define XGMAC_LPI_TIMER 0x0000002C /* LPI Timers Control */
#define XGMAC_TX_PACE 0x00000030 /* Transmit Pace and Stretch */
#define XGMAC_VLAN_HASH 0x00000034 /* VLAN Hash Table */
#define XGMAC_DEBUG 0x00000038 /* Debug */
#define XGMAC_INT_STAT 0x0000003C /* Interrupt and Control */
#define XGMAC_ADDR_HIGH(reg) (0x00000040 + ((reg) * 8))
#define XGMAC_ADDR_LOW(reg) (0x00000044 + ((reg) * 8))
#define XGMAC_HASH(n) (0x00000300 + (n) * 4) /* HASH table regs */
#define XGMAC_NUM_HASH 16
#define XGMAC_OMR 0x00000400
#define XGMAC_REMOTE_WAKE 0x00000700 /* Remote Wake-Up Frm Filter */
#define XGMAC_PMT 0x00000704 /* PMT Control and Status */
#define XGMAC_MMC_CTRL 0x00000800 /* XGMAC MMC Control */
#define XGMAC_MMC_INTR_RX 0x00000804 /* Recieve Interrupt */
#define XGMAC_MMC_INTR_TX 0x00000808 /* Transmit Interrupt */
#define XGMAC_MMC_INTR_MASK_RX 0x0000080c /* Recieve Interrupt Mask */
#define XGMAC_MMC_INTR_MASK_TX 0x00000810 /* Transmit Interrupt Mask */
/* Hardware TX Statistics Counters */
#define XGMAC_MMC_TXOCTET_GB_LO 0x00000814
#define XGMAC_MMC_TXOCTET_GB_HI 0x00000818
#define XGMAC_MMC_TXFRAME_GB_LO 0x0000081C
#define XGMAC_MMC_TXFRAME_GB_HI 0x00000820
#define XGMAC_MMC_TXBCFRAME_G 0x00000824
#define XGMAC_MMC_TXMCFRAME_G 0x0000082C
#define XGMAC_MMC_TXUCFRAME_GB 0x00000864
#define XGMAC_MMC_TXMCFRAME_GB 0x0000086C
#define XGMAC_MMC_TXBCFRAME_GB 0x00000874
#define XGMAC_MMC_TXUNDERFLOW 0x0000087C
#define XGMAC_MMC_TXOCTET_G_LO 0x00000884
#define XGMAC_MMC_TXOCTET_G_HI 0x00000888
#define XGMAC_MMC_TXFRAME_G_LO 0x0000088C
#define XGMAC_MMC_TXFRAME_G_HI 0x00000890
#define XGMAC_MMC_TXPAUSEFRAME 0x00000894
#define XGMAC_MMC_TXVLANFRAME 0x0000089C
/* Hardware RX Statistics Counters */
#define XGMAC_MMC_RXFRAME_GB_LO 0x00000900
#define XGMAC_MMC_RXFRAME_GB_HI 0x00000904
#define XGMAC_MMC_RXOCTET_GB_LO 0x00000908
#define XGMAC_MMC_RXOCTET_GB_HI 0x0000090C
#define XGMAC_MMC_RXOCTET_G_LO 0x00000910
#define XGMAC_MMC_RXOCTET_G_HI 0x00000914
#define XGMAC_MMC_RXBCFRAME_G 0x00000918
#define XGMAC_MMC_RXMCFRAME_G 0x00000920
#define XGMAC_MMC_RXCRCERR 0x00000928
#define XGMAC_MMC_RXRUNT 0x00000930
#define XGMAC_MMC_RXJABBER 0x00000934
#define XGMAC_MMC_RXUCFRAME_G 0x00000970
#define XGMAC_MMC_RXLENGTHERR 0x00000978
#define XGMAC_MMC_RXPAUSEFRAME 0x00000988
#define XGMAC_MMC_RXOVERFLOW 0x00000990
#define XGMAC_MMC_RXVLANFRAME 0x00000998
#define XGMAC_MMC_RXWATCHDOG 0x000009a0
/* DMA Control and Status Registers */
#define XGMAC_DMA_BUS_MODE 0x00000f00 /* Bus Mode */
#define XGMAC_DMA_TX_POLL 0x00000f04 /* Transmit Poll Demand */
#define XGMAC_DMA_RX_POLL 0x00000f08 /* Received Poll Demand */
#define XGMAC_DMA_RX_BASE_ADDR 0x00000f0c /* Receive List Base */
#define XGMAC_DMA_TX_BASE_ADDR 0x00000f10 /* Transmit List Base */
#define XGMAC_DMA_STATUS 0x00000f14 /* Status Register */
#define XGMAC_DMA_CONTROL 0x00000f18 /* Ctrl (Operational Mode) */
#define XGMAC_DMA_INTR_ENA 0x00000f1c /* Interrupt Enable */
#define XGMAC_DMA_MISS_FRAME_CTR 0x00000f20 /* Missed Frame Counter */
#define XGMAC_DMA_RI_WDOG_TIMER 0x00000f24 /* RX Intr Watchdog Timer */
#define XGMAC_DMA_AXI_BUS 0x00000f28 /* AXI Bus Mode */
#define XGMAC_DMA_AXI_STATUS 0x00000f2C /* AXI Status */
#define XGMAC_DMA_HW_FEATURE 0x00000f58 /* Enabled Hardware Features */
#define XGMAC_ADDR_AE 0x80000000
#define XGMAC_MAX_FILTER_ADDR 31
/* PMT Control and Status */
#define XGMAC_PMT_POINTER_RESET 0x80000000
#define XGMAC_PMT_GLBL_UNICAST 0x00000200
#define XGMAC_PMT_WAKEUP_RX_FRM 0x00000040
#define XGMAC_PMT_MAGIC_PKT 0x00000020
#define XGMAC_PMT_WAKEUP_FRM_EN 0x00000004
#define XGMAC_PMT_MAGIC_PKT_EN 0x00000002
#define XGMAC_PMT_POWERDOWN 0x00000001
#define XGMAC_CONTROL_SPD 0x40000000 /* Speed control */
#define XGMAC_CONTROL_SPD_MASK 0x60000000
#define XGMAC_CONTROL_SPD_1G 0x60000000
#define XGMAC_CONTROL_SPD_2_5G 0x40000000
#define XGMAC_CONTROL_SPD_10G 0x00000000
#define XGMAC_CONTROL_SARC 0x10000000 /* Source Addr Insert/Replace */
#define XGMAC_CONTROL_SARK_MASK 0x18000000
#define XGMAC_CONTROL_CAR 0x04000000 /* CRC Addition/Replacement */
#define XGMAC_CONTROL_CAR_MASK 0x06000000
#define XGMAC_CONTROL_DP 0x01000000 /* Disable Padding */
#define XGMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on rx */
#define XGMAC_CONTROL_JD 0x00400000 /* Jabber disable */
#define XGMAC_CONTROL_JE 0x00100000 /* Jumbo frame */
#define XGMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
#define XGMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */
#define XGMAC_CONTROL_ACS 0x00000080 /* Automatic Pad/FCS Strip */
#define XGMAC_CONTROL_DDIC 0x00000010 /* Disable Deficit Idle Count */
#define XGMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */
#define XGMAC_CONTROL_RE 0x00000004 /* Receiver Enable */
/* XGMAC Frame Filter defines */
#define XGMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */
#define XGMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */
#define XGMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */
#define XGMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */
#define XGMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */
#define XGMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */
#define XGMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */
#define XGMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */
#define XGMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */
#define XGMAC_FRAME_FILTER_VHF 0x00000800 /* VLAN Hash Filter */
#define XGMAC_FRAME_FILTER_VPF 0x00001000 /* VLAN Perfect Filter */
#define XGMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */
/* XGMAC FLOW CTRL defines */
#define XGMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */
#define XGMAC_FLOW_CTRL_PT_SHIFT 16
#define XGMAC_FLOW_CTRL_DZQP 0x00000080 /* Disable Zero-Quanta Phase */
#define XGMAC_FLOW_CTRL_PLT 0x00000020 /* Pause Low Threshhold */
#define XGMAC_FLOW_CTRL_PLT_MASK 0x00000030 /* PLT MASK */
#define XGMAC_FLOW_CTRL_UP 0x00000008 /* Unicast Pause Frame Detect */
#define XGMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */
#define XGMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */
#define XGMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */
/* XGMAC_INT_STAT reg */
#define XGMAC_INT_STAT_PMTIM 0x00800000 /* PMT Interrupt Mask */
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#define XGMAC_INT_STAT_PMT 0x0080 /* PMT Interrupt Status */
#define XGMAC_INT_STAT_LPI 0x0040 /* LPI Interrupt Status */
/* DMA Bus Mode register defines */
#define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */
#define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */
#define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */
#define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */
/* Programmable burst length */
#define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */
#define DMA_BUS_MODE_PBL_SHIFT 8
#define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */
#define DMA_BUS_MODE_RPBL_MASK 0x003e0000 /* Rx-Programmable Burst Len */
#define DMA_BUS_MODE_RPBL_SHIFT 17
#define DMA_BUS_MODE_USP 0x00800000
#define DMA_BUS_MODE_8PBL 0x01000000
#define DMA_BUS_MODE_AAL 0x02000000
/* DMA Bus Mode register defines */
#define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */
#define DMA_BUS_PR_RATIO_SHIFT 14
#define DMA_BUS_FB 0x00010000 /* Fixed Burst */
/* DMA Control register defines */
#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
#define DMA_CONTROL_DFF 0x01000000 /* Disable flush of rx frames */
#define DMA_CONTROL_OSF 0x00000004 /* Operate on 2nd tx frame */
/* DMA Normal interrupt */
#define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
#define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
#define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
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