Commit 04022982 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: switch to common helper to read bios from rom 



create a common helper function for soc15 and onwards
to read bios image from rom

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 381519df

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+2 −1
Original line number Diff line number Diff line
@@ -372,7 +372,8 @@ int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 
 */

bool amdgpu_get_bios(struct amdgpu_device *adev);

bool amdgpu_read_bios(struct amdgpu_device *adev);



bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,

				     u8 *bios, u32 length_bytes);

/*

 * Clocks

 */

drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c

+38 −0
Original line number Diff line number Diff line
@@ -464,3 +464,41 @@ bool amdgpu_get_bios(struct amdgpu_device *adev) 
	adev->is_atom_fw = (adev->asic_type >= CHIP_VEGA10) ? true : false;

	return true;

}



/* helper function for soc15 and onwards to read bios from rom */

bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,

				     u8 *bios, u32 length_bytes)

{

	u32 *dw_ptr;

	u32 i, length_dw;

	u32 rom_index_offset;

	u32 rom_data_offset;



	if (bios == NULL)

		return false;

	if (length_bytes == 0)

		return false;

	/* APU vbios image is part of sbios image */

	if (adev->flags & AMD_IS_APU)

		return false;

	if (!adev->smuio.funcs ||

	    !adev->smuio.funcs->get_rom_index_offset ||

	    !adev->smuio.funcs->get_rom_data_offset)

		return false;



	dw_ptr = (u32 *)bios;

	length_dw = ALIGN(length_bytes, 4) / 4;



	rom_index_offset =

		adev->smuio.funcs->get_rom_index_offset(adev);

	rom_data_offset =

		adev->smuio.funcs->get_rom_data_offset(adev);



	/* set rom index to 0 */

	WREG32(rom_index_offset, 0);

	/* read out the rom data */

	for (i = 0; i < length_dw; i++)

		dw_ptr[i] = RREG32(rom_data_offset);



	return true;

}

drivers/gpu/drm/amd/amdgpu/nv.c

+1 −33
Original line number Diff line number Diff line
@@ -330,38 +330,6 @@ static bool nv_read_disabled_bios(struct amdgpu_device *adev) 
	return false;

}



static bool nv_read_bios_from_rom(struct amdgpu_device *adev,

				  u8 *bios, u32 length_bytes)

{

	u32 *dw_ptr;

	u32 i, length_dw;

	u32 rom_index_offset, rom_data_offset;



	if (bios == NULL)

		return false;

	if (length_bytes == 0)

		return false;

	/* APU vbios image is part of sbios image */

	if (adev->flags & AMD_IS_APU)

		return false;



	dw_ptr = (u32 *)bios;

	length_dw = ALIGN(length_bytes, 4) / 4;



	rom_index_offset =

		adev->smuio.funcs->get_rom_index_offset(adev);

	rom_data_offset =

		adev->smuio.funcs->get_rom_data_offset(adev);



	/* set rom index to 0 */

	WREG32(rom_index_offset, 0);

	/* read out the rom data */

	for (i = 0; i < length_dw; i++)

		dw_ptr[i] = RREG32(rom_data_offset);



	return true;

}



static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {

	{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},

	{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
@@ -678,7 +646,7 @@ static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 
static const struct amdgpu_asic_funcs nv_asic_funcs =

{

	.read_disabled_bios = &nv_read_disabled_bios,

	.read_bios_from_rom = &nv_read_bios_from_rom,

	.read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,

	.read_register = &nv_read_register,

	.reset = &nv_asic_reset,

	.reset_method = &nv_asic_reset_method,

drivers/gpu/drm/amd/amdgpu/soc15.c

+2 −35
Original line number Diff line number Diff line
@@ -375,39 +375,6 @@ static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 
	return false;

}



static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,

				     u8 *bios, u32 length_bytes)

{

	u32 *dw_ptr;

	u32 i, length_dw;

	uint32_t rom_index_offset;

	uint32_t rom_data_offset;



	if (bios == NULL)

		return false;

	if (length_bytes == 0)

		return false;

	/* APU vbios image is part of sbios image */

	if (adev->flags & AMD_IS_APU)

		return false;



	dw_ptr = (u32 *)bios;

	length_dw = ALIGN(length_bytes, 4) / 4;



	rom_index_offset =

		adev->smuio.funcs->get_rom_index_offset(adev);

	rom_data_offset =

		adev->smuio.funcs->get_rom_data_offset(adev);



	/* set rom index to 0 */

	WREG32(rom_index_offset, 0);

	/* read out the rom data */

	for (i = 0; i < length_dw; i++)

		dw_ptr[i] = RREG32(rom_data_offset);



	return true;

}



static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {

	{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},

	{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
@@ -925,7 +892,7 @@ static void soc15_pre_asic_init(struct amdgpu_device *adev) 
static const struct amdgpu_asic_funcs soc15_asic_funcs =

{

	.read_disabled_bios = &soc15_read_disabled_bios,

	.read_bios_from_rom = &soc15_read_bios_from_rom,

	.read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,

	.read_register = &soc15_read_register,

	.reset = &soc15_asic_reset,

	.reset_method = &soc15_asic_reset_method,
@@ -947,7 +914,7 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs = 
static const struct amdgpu_asic_funcs vega20_asic_funcs =

{

	.read_disabled_bios = &soc15_read_disabled_bios,

	.read_bios_from_rom = &soc15_read_bios_from_rom,

	.read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,

	.read_register = &soc15_read_register,

	.reset = &soc15_asic_reset,

	.reset_method = &soc15_asic_reset_method,