MIPS: BCM63XX: Add support for bcm6368 CPU. (04712f3f) · Commits · jan.koester / Linux

arch/mips/bcm63xx/Kconfig

+4 −0

Original line number	Original line	Diff line number	Diff line
	@@ -20,6 +20,10 @@ config BCM63XX_CPU_6348
	config BCM63XX_CPU_6358		config BCM63XX_CPU_6358
	bool "support 6358 CPU"		bool "support 6358 CPU"
	select HW_HAS_PCI		select HW_HAS_PCI

			config BCM63XX_CPU_6368
			bool "support 6368 CPU"
			select HW_HAS_PCI
	endmenu		endmenu

	source "arch/mips/bcm63xx/boards/Kconfig"		source "arch/mips/bcm63xx/boards/Kconfig"

arch/mips/bcm63xx/clk.c

+67 −3

Original line number	Original line	Diff line number	Diff line
	@@ -10,6 +10,7 @@
	#include <linux/mutex.h>		#include <linux/mutex.h>
	#include <linux/err.h>		#include <linux/err.h>
	#include <linux/clk.h>		#include <linux/clk.h>
			#include <linux/delay.h>
	#include <bcm63xx_cpu.h>		#include <bcm63xx_cpu.h>
	#include <bcm63xx_io.h>		#include <bcm63xx_io.h>
	#include <bcm63xx_regs.h>		#include <bcm63xx_regs.h>
	@@ -112,6 +113,34 @@ static struct clk clk_ephy = {
	.set = ephy_set,		.set = ephy_set,
	};		};

			/*
			* Ethernet switch clock
			*/
			static void enetsw_set(struct clk *clk, int enable)
			{
			if (!BCMCPU_IS_6368())
			return;
			bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN \|
			CKCTL_6368_SWPKT_USB_EN \|
			CKCTL_6368_SWPKT_SAR_EN, enable);
			if (enable) {
			u32 val;

			/* reset switch core afer clock change */
			val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
			val &= ~SOFTRESET_6368_ENETSW_MASK;
			bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
			msleep(10);
			val \|= SOFTRESET_6368_ENETSW_MASK;
			bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
			msleep(10);
			}
			}

			static struct clk clk_enetsw = {
			.set = enetsw_set,
			};

	/*		/*
	* PCM clock		* PCM clock
	*/		*/
	@@ -131,9 +160,10 @@ static struct clk clk_pcm = {
	*/		*/
	static void usbh_set(struct clk *clk, int enable)		static void usbh_set(struct clk *clk, int enable)
	{		{
	if (!BCMCPU_IS_6348())		if (BCMCPU_IS_6348())
	return;
	bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);		bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
			else if (BCMCPU_IS_6368())
			bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable);
	}		}

	static struct clk clk_usbh = {		static struct clk clk_usbh = {
	@@ -161,6 +191,36 @@ static struct clk clk_spi = {
	.set = spi_set,		.set = spi_set,
	};		};

			/*
			* XTM clock
			*/
			static void xtm_set(struct clk *clk, int enable)
			{
			if (!BCMCPU_IS_6368())
			return;

			bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN \|
			CKCTL_6368_SWPKT_SAR_EN, enable);

			if (enable) {
			u32 val;

			/* reset sar core afer clock change */
			val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
			val &= ~SOFTRESET_6368_SAR_MASK;
			bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
			mdelay(1);
			val \|= SOFTRESET_6368_SAR_MASK;
			bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
			mdelay(1);
			}
			}


			static struct clk clk_xtm = {
			.set = xtm_set,
			};

	/*		/*
	* Internal peripheral clock		* Internal peripheral clock
	*/		*/
	@@ -204,12 +264,16 @@ struct clk clk_get(struct device dev, const char *id)
	return &clk_enet0;		return &clk_enet0;
	if (!strcmp(id, "enet1"))		if (!strcmp(id, "enet1"))
	return &clk_enet1;		return &clk_enet1;
			if (!strcmp(id, "enetsw"))
			return &clk_enetsw;
	if (!strcmp(id, "ephy"))		if (!strcmp(id, "ephy"))
	return &clk_ephy;		return &clk_ephy;
	if (!strcmp(id, "usbh"))		if (!strcmp(id, "usbh"))
	return &clk_usbh;		return &clk_usbh;
	if (!strcmp(id, "spi"))		if (!strcmp(id, "spi"))
	return &clk_spi;		return &clk_spi;
			if (!strcmp(id, "xtm"))
			return &clk_xtm;
	if (!strcmp(id, "periph"))		if (!strcmp(id, "periph"))
	return &clk_periph;		return &clk_periph;
	if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))		if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))

arch/mips/bcm63xx/cpu.c

+63 −16

Original line number	Original line	Diff line number	Diff line
	@@ -63,6 +63,15 @@ static const int bcm6358_irqs[] = {

	};		};

			static const unsigned long bcm6368_regs_base[] = {
			__GEN_CPU_REGS_TABLE(6368)
			};

			static const int bcm6368_irqs[] = {
			__GEN_CPU_IRQ_TABLE(6368)

			};

	u16 __bcm63xx_get_cpu_id(void)		u16 __bcm63xx_get_cpu_id(void)
	{		{
	return bcm63xx_cpu_id;		return bcm63xx_cpu_id;
	@@ -89,20 +98,19 @@ unsigned int bcm63xx_get_memory_size(void)

	static unsigned int detect_cpu_clock(void)		static unsigned int detect_cpu_clock(void)
	{		{
	unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;		switch (bcm63xx_get_cpu_id()) {
			case BCM6338_CPU_ID:
	/* BCM6338 has a fixed 240 Mhz frequency */		/* BCM6338 has a fixed 240 Mhz frequency */
	if (BCMCPU_IS_6338())
	return 240000000;		return 240000000;

			case BCM6345_CPU_ID:
	/* BCM6345 has a fixed 140Mhz frequency */		/* BCM6345 has a fixed 140Mhz frequency */
	if (BCMCPU_IS_6345())
	return 140000000;		return 140000000;

	/*		case BCM6348_CPU_ID:
	* frequency depends on PLL configuration:		{
	*/		unsigned int tmp, n1, n2, m1;
	if (BCMCPU_IS_6348()) {
	/* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */		/* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
	tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);		tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
	n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;		n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
	@@ -111,17 +119,47 @@ static unsigned int detect_cpu_clock(void)
	n1 += 1;		n1 += 1;
	n2 += 2;		n2 += 2;
	m1 += 1;		m1 += 1;
			return (16 * 1000000 * n1 * n2) / m1;
	}		}

	if (BCMCPU_IS_6358()) {		case BCM6358_CPU_ID:
			{
			unsigned int tmp, n1, n2, m1;

	/* 16MHz * N1 * N2 / M1_CPU */		/* 16MHz * N1 * N2 / M1_CPU */
	tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);		tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
	n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;		n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
	n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;		n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
	m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;		m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
			return (16 * 1000000 * n1 * n2) / m1;
	}		}

	return (16 * 1000000 * n1 * n2) / m1;		case BCM6368_CPU_ID:
			{
			unsigned int tmp, p1, p2, ndiv, m1;

			/* (64MHz / P1) * P2 * NDIV / M1_CPU */
			tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG);

			p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >>
			DMIPSPLLCFG_6368_P1_SHIFT;

			p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >>
			DMIPSPLLCFG_6368_P2_SHIFT;

			ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
			DMIPSPLLCFG_6368_NDIV_SHIFT;

			tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG);
			m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >>
			DMIPSPLLDIV_6368_MDIV_SHIFT;

			return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
			}

			default:
			BUG();
			}
	}		}

	/*		/*
	@@ -143,7 +181,7 @@ static unsigned int detect_memory_size(void)
	banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;		banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
	}		}

	if (BCMCPU_IS_6358()) {		if (BCMCPU_IS_6358() \|\| BCMCPU_IS_6368()) {
	val = bcm_memc_readl(MEMC_CFG_REG);		val = bcm_memc_readl(MEMC_CFG_REG);
	rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;		rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
	cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;		cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
	@@ -188,10 +226,19 @@ void __init bcm63xx_cpu_init(void)
	bcm63xx_irqs = bcm6345_irqs;		bcm63xx_irqs = bcm6345_irqs;
	break;		break;
	case CPU_BMIPS4350:		case CPU_BMIPS4350:
			switch (read_c0_prid() & 0xf0) {
			case 0x10:
	expected_cpu_id = BCM6358_CPU_ID;		expected_cpu_id = BCM6358_CPU_ID;
	bcm63xx_regs_base = bcm6358_regs_base;		bcm63xx_regs_base = bcm6358_regs_base;
	bcm63xx_irqs = bcm6358_irqs;		bcm63xx_irqs = bcm6358_irqs;
	break;		break;
			case 0x30:
			expected_cpu_id = BCM6368_CPU_ID;
			bcm63xx_regs_base = bcm6368_regs_base;
			bcm63xx_irqs = bcm6368_irqs;
			break;
			}
			break;
	}		}

	/*		/*

arch/mips/bcm63xx/dev-uart.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -54,7 +54,7 @@ int __init bcm63xx_uart_register(unsigned int id)
	if (id >= ARRAY_SIZE(bcm63xx_uart_devices))		if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
	return -ENODEV;		return -ENODEV;

	if (id == 1 && !BCMCPU_IS_6358())		if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()))
	return -ENODEV;		return -ENODEV;

	if (id == 0) {		if (id == 0) {

arch/mips/bcm63xx/irq.c

+23 −1

Original line number	Original line	Diff line number	Diff line
	@@ -71,6 +71,17 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
	#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358		#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358
	#define ext_irq_cfg_reg2 0		#define ext_irq_cfg_reg2 0
	#endif		#endif
			#ifdef CONFIG_BCM63XX_CPU_6368
			#define irq_stat_reg PERF_IRQSTAT_6368_REG
			#define irq_mask_reg PERF_IRQMASK_6368_REG
			#define irq_bits 64
			#define is_ext_irq_cascaded 1
			#define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
			#define ext_irq_end (BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE)
			#define ext_irq_count 6
			#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6368
			#define ext_irq_cfg_reg2 PERF_EXTIRQ_CFG_REG2_6368
			#endif

	#if irq_bits == 32		#if irq_bits == 32
	#define dispatch_internal __dispatch_internal		#define dispatch_internal __dispatch_internal
	@@ -134,6 +145,17 @@ static void bcm63xx_init_irq(void)
	ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;		ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
	ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
	break;		break;
			case BCM6368_CPU_ID:
			irq_stat_addr += PERF_IRQSTAT_6368_REG;
			irq_mask_addr += PERF_IRQMASK_6368_REG;
			irq_bits = 64;
			ext_irq_count = 6;
			is_ext_irq_cascaded = 1;
			ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
			ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
			ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
			ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
			break;
	default:		default:
	BUG();		BUG();
	}		}
	@@ -406,7 +428,7 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
	reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);		reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
	}		}

	if (BCMCPU_IS_6338() \|\| BCMCPU_IS_6358()) {		if (BCMCPU_IS_6338() \|\| BCMCPU_IS_6358() \|\| BCMCPU_IS_6368()) {
	if (levelsense)		if (levelsense)
	reg \|= EXTIRQ_CFG_LEVELSENSE(irq);		reg \|= EXTIRQ_CFG_LEVELSENSE(irq);
	else		else