Loading Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +0 −8 Original line number Diff line number Diff line Loading @@ -4,7 +4,6 @@ Required properties: - compatible: Must be "ti,<soc>-ehrpwm". for am33xx - compatible = "ti,am33xx-ehrpwm"; for da850 - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; for dra7xx - compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. Loading @@ -28,10 +27,3 @@ ehrpwm0: ehrpwm@0 { /* EHRPWM on da850 */ #pwm-cells = <3>; reg = <0x300000 0x2000>; }; ehrpwm0: ehrpwm@0 { /* EHRPWM on dra7xx */ compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48440200 0x80>; ti,hwmods = "ehrpwm0"; }; Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt +1 −16 Original line number Diff line number Diff line TI SOC based PWM Subsystem Required properties: - compatible: Must be "ti,<soc>-pwmss". for am33xx - compatible = "ti,am33xx-pwmss" for dra7xx - compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss" - compatible: Must be "ti,am33xx-pwmss"; - reg: physical base address and size of the registers map. - address-cells: Specify the number of u32 entries needed in child nodes. Should set to 1. Loading Loading @@ -31,16 +29,3 @@ pwmss0: pwmss@48300000 { /* child nodes go here */ }; epwmss0: epwmss@4843e000 { /* On DRA7xx */ compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"; reg = <0x4843e000 0x30>; ti,hwmods = "epwmss0"; #address-cells = <1>; #size-cells = <1>; ranges = <0x4843e100 0x4843e100 0x80 /* ECAP */ 0x4843e180 0x4843e180 0x80 /* EQEP */ 0x4843e200 0x4843e200 0x80>; /* EHRPWM */ /* child nodes go here */ }; arch/arm/boot/dts/dra7.dtsi +0 −64 Original line number Diff line number Diff line Loading @@ -1563,70 +1563,6 @@ hdmi: encoder@58060000 { clock-names = "fck", "sys_clk"; }; }; epwmss0: epwmss@4843e000 { compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"; reg = <0x4843e000 0x30>; ti,hwmods = "epwmss0"; #address-cells = <1>; #size-cells = <1>; status = "disabled"; ranges = <0x4843e100 0x4843e100 0x80 /* ECAP */ 0x4843e180 0x4843e180 0x80 /* EQEP */ 0x4843e200 0x4843e200 0x80>;/* EHRPWM */ ehrpwm0: ehrpwm@4843e200 { compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x4843e200 0x80>; ti,hwmods = "ehrpwm0"; status = "disabled"; }; }; epwmss1: epwmss@48440000 { compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"; reg = <0x48440000 0x30>; ti,hwmods = "epwmss1"; #address-cells = <1>; #size-cells = <1>; status = "disabled"; ranges = <0x48440100 0x48440100 0x80 /* ECAP */ 0x48440180 0x48440180 0x80 /* EQEP */ 0x48440200 0x48440200 0x80>; /* EHRPWM */ ehrpwm1: ehrpwm@48440200 { compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48440200 0x80>; ti,hwmods = "ehrpwm1"; status = "disabled"; }; }; epwmss2: epwmss@48442000 { compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"; reg = <0x48442000 0x30>; ti,hwmods = "epwmss2"; #address-cells = <1>; #size-cells = <1>; status = "disabled"; ranges = <0x48442100 0x48442100 0x80 /* ECAP */ 0x48442180 0x48442180 0x80 /* EQEP */ 0x48442200 0x48442200 0x80>; /* EHRPWM */ ehrpwm2: ehrpwm@48442200 { compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48442200 0x80>; ti,hwmods = "ehrpwm2"; status = "disabled"; }; }; }; thermal_zones: thermal-zones { Loading Loading
Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +0 −8 Original line number Diff line number Diff line Loading @@ -4,7 +4,6 @@ Required properties: - compatible: Must be "ti,<soc>-ehrpwm". for am33xx - compatible = "ti,am33xx-ehrpwm"; for da850 - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; for dra7xx - compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. Loading @@ -28,10 +27,3 @@ ehrpwm0: ehrpwm@0 { /* EHRPWM on da850 */ #pwm-cells = <3>; reg = <0x300000 0x2000>; }; ehrpwm0: ehrpwm@0 { /* EHRPWM on dra7xx */ compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48440200 0x80>; ti,hwmods = "ehrpwm0"; };
Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt +1 −16 Original line number Diff line number Diff line TI SOC based PWM Subsystem Required properties: - compatible: Must be "ti,<soc>-pwmss". for am33xx - compatible = "ti,am33xx-pwmss" for dra7xx - compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss" - compatible: Must be "ti,am33xx-pwmss"; - reg: physical base address and size of the registers map. - address-cells: Specify the number of u32 entries needed in child nodes. Should set to 1. Loading Loading @@ -31,16 +29,3 @@ pwmss0: pwmss@48300000 { /* child nodes go here */ }; epwmss0: epwmss@4843e000 { /* On DRA7xx */ compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"; reg = <0x4843e000 0x30>; ti,hwmods = "epwmss0"; #address-cells = <1>; #size-cells = <1>; ranges = <0x4843e100 0x4843e100 0x80 /* ECAP */ 0x4843e180 0x4843e180 0x80 /* EQEP */ 0x4843e200 0x4843e200 0x80>; /* EHRPWM */ /* child nodes go here */ };
arch/arm/boot/dts/dra7.dtsi +0 −64 Original line number Diff line number Diff line Loading @@ -1563,70 +1563,6 @@ hdmi: encoder@58060000 { clock-names = "fck", "sys_clk"; }; }; epwmss0: epwmss@4843e000 { compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"; reg = <0x4843e000 0x30>; ti,hwmods = "epwmss0"; #address-cells = <1>; #size-cells = <1>; status = "disabled"; ranges = <0x4843e100 0x4843e100 0x80 /* ECAP */ 0x4843e180 0x4843e180 0x80 /* EQEP */ 0x4843e200 0x4843e200 0x80>;/* EHRPWM */ ehrpwm0: ehrpwm@4843e200 { compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x4843e200 0x80>; ti,hwmods = "ehrpwm0"; status = "disabled"; }; }; epwmss1: epwmss@48440000 { compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"; reg = <0x48440000 0x30>; ti,hwmods = "epwmss1"; #address-cells = <1>; #size-cells = <1>; status = "disabled"; ranges = <0x48440100 0x48440100 0x80 /* ECAP */ 0x48440180 0x48440180 0x80 /* EQEP */ 0x48440200 0x48440200 0x80>; /* EHRPWM */ ehrpwm1: ehrpwm@48440200 { compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48440200 0x80>; ti,hwmods = "ehrpwm1"; status = "disabled"; }; }; epwmss2: epwmss@48442000 { compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"; reg = <0x48442000 0x30>; ti,hwmods = "epwmss2"; #address-cells = <1>; #size-cells = <1>; status = "disabled"; ranges = <0x48442100 0x48442100 0x80 /* ECAP */ 0x48442180 0x48442180 0x80 /* EQEP */ 0x48442200 0x48442200 0x80>; /* EHRPWM */ ehrpwm2: ehrpwm@48442200 { compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48442200 0x80>; ti,hwmods = "ehrpwm2"; status = "disabled"; }; }; }; thermal_zones: thermal-zones { Loading