Commit 04eb3d1c authored by Russell King (Oracle)'s avatar Russell King (Oracle) Committed by Paolo Abeni
Browse files

net: mtk_eth_soc: tidy mtk_gmac0_rgmii_adjust() 



Get rid of the multiple tenary operators in mtk_gmac0_rgmii_adjust()
replacing them with a single if(), thus making the code easier to read.

Signed-off-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent 7e01b408

drivers/net/ethernet/mediatek/mtk_eth_soc.c

+19 −15
Original line number Original line Diff line number Diff line
@@ -397,38 +397,42 @@ static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 
static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,

static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,

				   phy_interface_t interface, int speed)

				   phy_interface_t interface, int speed)

{

{

	u32 val;

	unsigned long rate;

	u32 tck, rck, intf;

	int ret;

	int ret;





	if (interface == PHY_INTERFACE_MODE_TRGMII) {

	if (interface == PHY_INTERFACE_MODE_TRGMII) {

		mtk_w32(eth, TRGMII_MODE, INTF_MODE);

		mtk_w32(eth, TRGMII_MODE, INTF_MODE);

		val = 500000000;

		ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], 500000000);

		ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);

		if (ret)

		if (ret)

			dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);

			dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);

		return;

		return;

	}

	}





	val = (speed == SPEED_1000) ?

	if (speed == SPEED_1000) {

		INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;

		intf = INTF_MODE_RGMII_1000;

	mtk_w32(eth, val, INTF_MODE);

		rate = 250000000;

		rck = RCK_CTRL_RGMII_1000;

		tck = TCK_CTRL_RGMII_1000;

	} else {

		intf = INTF_MODE_RGMII_10_100;

		rate = 500000000;

		rck = RCK_CTRL_RGMII_10_100;

		tck = TCK_CTRL_RGMII_10_100;

	}



	mtk_w32(eth, intf, INTF_MODE);





	regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,

	regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,

			   ETHSYS_TRGMII_CLK_SEL362_5,

			   ETHSYS_TRGMII_CLK_SEL362_5,

			   ETHSYS_TRGMII_CLK_SEL362_5);

			   ETHSYS_TRGMII_CLK_SEL362_5);





	val = (speed == SPEED_1000) ? 250000000 : 500000000;

	ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], rate);

	ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);

	if (ret)

	if (ret)

		dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);

		dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);





	val = (speed == SPEED_1000) ?

	mtk_w32(eth, rck, TRGMII_RCK_CTRL);

		RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;

	mtk_w32(eth, tck, TRGMII_TCK_CTRL);

	mtk_w32(eth, val, TRGMII_RCK_CTRL);



	val = (speed == SPEED_1000) ?

		TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;

	mtk_w32(eth, val, TRGMII_TCK_CTRL);

}

}





static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,

static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,