Commit 05b4ebd2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm 

Pull kvm fixes from Paolo Bonzini:
 "RISC-V:

   - Fix compilation without RISCV_ISA_ZICBOM

   - Fix kvm_riscv_vcpu_timer_pending() for Sstc

  ARM:

   - Fix a bug preventing restoring an ITS containing mappings for very
     large and very sparse device topology

   - Work around a relocation handling error when compiling the nVHE
     object with profile optimisation

   - Fix for stage-2 invalidation holding the VM MMU lock for too long
     by limiting the walk to the largest block mapping size

   - Enable stack protection and branch profiling for VHE

   - Two selftest fixes

  x86:

   - add compat implementation for KVM_X86_SET_MSR_FILTER ioctl

  selftests:

   - synchronize includes between include/uapi and tools/include/uapi"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
  tools: include: sync include/api/linux/kvm.h
  KVM: x86: Add compat handler for KVM_X86_SET_MSR_FILTER
  KVM: x86: Copy filter arg outside kvm_vm_ioctl_set_msr_filter()
  kvm: Add support for arch compat vm ioctls
  RISC-V: KVM: Fix kvm_riscv_vcpu_timer_pending() for Sstc
  RISC-V: Fix compilation without RISCV_ISA_ZICBOM
  KVM: arm64: vgic: Fix exit condition in scan_its_table()
  KVM: arm64: nvhe: Fix build with profile optimization
  KVM: selftests: Fix number of pages for memory slot in memslot_modification_stress_test
  KVM: arm64: selftests: Fix multiple versions of GIC creation
  KVM: arm64: Enable stack protection and branch profiling for VHE
  KVM: arm64: Limit stage2_apply_range() batch size to largest block
  KVM: arm64: Work out supported block level at compile time
parents ca4582c2 9aec606c

arch/arm64/include/asm/kvm_pgtable.h

+13 −5
Original line number Diff line number Diff line
@@ -13,6 +13,18 @@ 


#define KVM_PGTABLE_MAX_LEVELS		4U



/*

 * The largest supported block sizes for KVM (no 52-bit PA support):

 *  - 4K (level 1):	1GB

 *  - 16K (level 2):	32MB

 *  - 64K (level 2):	512MB

 */

#ifdef CONFIG_ARM64_4K_PAGES

#define KVM_PGTABLE_MIN_BLOCK_LEVEL	1U

#else

#define KVM_PGTABLE_MIN_BLOCK_LEVEL	2U

#endif



static inline u64 kvm_get_parange(u64 mmfr0)

{

	u64 parange = cpuid_feature_extract_unsigned_field(mmfr0,
@@ -58,11 +70,7 @@ static inline u64 kvm_granule_size(u32 level) 


static inline bool kvm_level_supports_block_mapping(u32 level)

{

	/*

	 * Reject invalid block mappings and don't bother with 4TB mappings for

	 * 52-bit PAs.

	 */

	return !(level == 0 || (PAGE_SIZE != SZ_4K && level == 1));

	return level >= KVM_PGTABLE_MIN_BLOCK_LEVEL;

}



/**

arch/arm64/include/asm/stage2_pgtable.h

+0 −20
Original line number Diff line number Diff line
@@ -10,13 +10,6 @@ 


#include <linux/pgtable.h>



/*

 * PGDIR_SHIFT determines the size a top-level page table entry can map

 * and depends on the number of levels in the page table. Compute the

 * PGDIR_SHIFT for a given number of levels.

 */

#define pt_levels_pgdir_shift(lvls)	ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - (lvls))



/*

 * The hardware supports concatenation of up to 16 tables at stage2 entry

 * level and we use the feature whenever possible, which means we resolve 4
@@ -30,11 +23,6 @@ 
#define stage2_pgtable_levels(ipa)	ARM64_HW_PGTABLE_LEVELS((ipa) - 4)

#define kvm_stage2_levels(kvm)		VTCR_EL2_LVLS(kvm->arch.vtcr)



/* stage2_pgdir_shift() is the size mapped by top-level stage2 entry for the VM */

#define stage2_pgdir_shift(kvm)		pt_levels_pgdir_shift(kvm_stage2_levels(kvm))

#define stage2_pgdir_size(kvm)		(1ULL << stage2_pgdir_shift(kvm))

#define stage2_pgdir_mask(kvm)		~(stage2_pgdir_size(kvm) - 1)



/*

 * kvm_mmmu_cache_min_pages() is the number of pages required to install

 * a stage-2 translation. We pre-allocate the entry level page table at
@@ -42,12 +30,4 @@ 
 */

#define kvm_mmu_cache_min_pages(kvm)	(kvm_stage2_levels(kvm) - 1)



static inline phys_addr_t

stage2_pgd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end)

{

	phys_addr_t boundary = (addr + stage2_pgdir_size(kvm)) & stage2_pgdir_mask(kvm);



	return (boundary - 1 < end - 1) ? boundary : end;

}



#endif	/* __ARM64_S2_PGTABLE_H_ */

arch/arm64/kvm/hyp/Makefile

+1 −4
Original line number Diff line number Diff line
@@ -5,9 +5,6 @@ 


incdir := $(srctree)/$(src)/include

subdir-asflags-y := -I$(incdir)

subdir-ccflags-y := -I$(incdir)				\

		    -fno-stack-protector		\

		    -DDISABLE_BRANCH_PROFILING		\

		    $(DISABLE_STACKLEAK_PLUGIN)

subdir-ccflags-y := -I$(incdir)



obj-$(CONFIG_KVM) += vhe/ nvhe/ pgtable.o

arch/arm64/kvm/hyp/nvhe/Makefile

+7 −0
Original line number Diff line number Diff line
@@ -10,6 +10,9 @@ asflags-y := -D__KVM_NVHE_HYPERVISOR__ -D__DISABLE_EXPORTS 
# will explode instantly (Words of Marc Zyngier). So introduce a generic flag

# __DISABLE_TRACE_MMIO__ to disable MMIO tracing for nVHE KVM.

ccflags-y := -D__KVM_NVHE_HYPERVISOR__ -D__DISABLE_EXPORTS -D__DISABLE_TRACE_MMIO__

ccflags-y += -fno-stack-protector	\

	     -DDISABLE_BRANCH_PROFILING	\

	     $(DISABLE_STACKLEAK_PLUGIN)



hostprogs := gen-hyprel

HOST_EXTRACFLAGS += -I$(objtree)/include
@@ -89,6 +92,10 @@ quiet_cmd_hypcopy = HYPCOPY $@ 
# Remove ftrace, Shadow Call Stack, and CFI CFLAGS.

# This is equivalent to the 'notrace', '__noscs', and '__nocfi' annotations.

KBUILD_CFLAGS := $(filter-out $(CC_FLAGS_FTRACE) $(CC_FLAGS_SCS) $(CC_FLAGS_CFI), $(KBUILD_CFLAGS))

# Starting from 13.0.0 llvm emits SHT_REL section '.llvm.call-graph-profile'

# when profile optimization is applied. gen-hyprel does not support SHT_REL and

# causes a build failure. Remove profile optimization flags.

KBUILD_CFLAGS := $(filter-out -fprofile-sample-use=% -fprofile-use=%, $(KBUILD_CFLAGS))



# KVM nVHE code is run at a different exception code with a different map, so

# compiler instrumentation that inserts callbacks or checks into the code may

arch/arm64/kvm/mmu.c

+8 −1
Original line number Diff line number Diff line
@@ -31,6 +31,13 @@ static phys_addr_t hyp_idmap_vector; 


static unsigned long io_map_base;



static phys_addr_t stage2_range_addr_end(phys_addr_t addr, phys_addr_t end)

{

	phys_addr_t size = kvm_granule_size(KVM_PGTABLE_MIN_BLOCK_LEVEL);

	phys_addr_t boundary = ALIGN_DOWN(addr + size, size);



	return (boundary - 1 < end - 1) ? boundary : end;

}



/*

 * Release kvm_mmu_lock periodically if the memory region is large. Otherwise,
@@ -52,7 +59,7 @@ static int stage2_apply_range(struct kvm *kvm, phys_addr_t addr, 
		if (!pgt)

			return -EINVAL;



		next = stage2_pgd_addr_end(kvm, addr, end);

		next = stage2_range_addr_end(addr, end);

		ret = fn(pgt, addr, next - addr);

		if (ret)

			break;