Commit 05d11e2f authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: rzg2l: Add clock-names and reset-names to DMAC nodes 



Add clock-names and reset-names to RZ/G2{L,LC,UL}, RZ/V2L and
RZ/Five DMAC nodes.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230315064726.22739-2-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 4db0ce40

arch/arm64/boot/dts/renesas/r9a07g043.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -564,9 +564,11 @@ dmac: dma-controller@11820000 { 
					  "ch12", "ch13", "ch14", "ch15";

			clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>,

				 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>;

			clock-names = "main", "register";

			power-domains = <&cpg>;

			resets = <&cpg R9A07G043_DMAC_ARESETN>,

				 <&cpg R9A07G043_DMAC_RST_ASYNC>;

			reset-names = "arst", "rst_async";

			#dma-cells = <1>;

			dma-channels = <16>;

		};

arch/arm64/boot/dts/renesas/r9a07g044.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -740,9 +740,11 @@ dmac: dma-controller@11820000 { 
					  "ch12", "ch13", "ch14", "ch15";

			clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,

				 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;

			clock-names = "main", "register";

			power-domains = <&cpg>;

			resets = <&cpg R9A07G044_DMAC_ARESETN>,

				 <&cpg R9A07G044_DMAC_RST_ASYNC>;

			reset-names = "arst", "rst_async";

			#dma-cells = <1>;

			dma-channels = <16>;

		};

arch/arm64/boot/dts/renesas/r9a07g054.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -746,9 +746,11 @@ dmac: dma-controller@11820000 { 
					  "ch12", "ch13", "ch14", "ch15";

			clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,

				 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>;

			clock-names = "main", "register";

			power-domains = <&cpg>;

			resets = <&cpg R9A07G054_DMAC_ARESETN>,

				 <&cpg R9A07G054_DMAC_RST_ASYNC>;

			reset-names = "arst", "rst_async";

			#dma-cells = <1>;

			dma-channels = <16>;

		};