Commit 074efb5c authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
Browse files

drm/amd/display: Check minimum disp_clk and dpp_clk debug option 



Our debug struct has the min_disp_clk_khz and min_dpp_clk_khz options,
which we ignore in the DCN32. This commit introduces those checks and
the necessary calculation.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarAurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a30e8c13

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

+19 −0
Original line number Diff line number Diff line
@@ -265,6 +265,25 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) 
			&clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,

			&num_levels);



	if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {

		unsigned int i;



		for (i = 0; i < num_levels; i++)

			if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz

					< khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))

				clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz

					= khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);

	}



	if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {

		unsigned int i;



		for (i = 0; i < num_levels; i++)

			if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz

					< khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))

				clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz

					= khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);

	}



	/* Get UCLK, update bounding box */

	clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);