Commit 079926b5 authored by Johan Hovold's avatar Johan Hovold Committed by Bjorn Andersson
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ARM: dts: qcom: sdx65: reorder USB interrupts 



Three SoCs did not follow the interrupt order specified by the USB
controller binding.

While keeping the non-SuperSpeed interrupts together seems natural,
reorder the interrupts to match the binding.

Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarJohan Hovold <johan+linaro@kernel.org>
[bjorn: Split out from arm64 patch]
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220715070248.19078-5-johan+linaro@kernel.org
parent 5142c392

arch/arm/boot/dts/qcom-sdx65.dtsi

+6 −4
Original line number Diff line number Diff line
@@ -372,11 +372,13 @@ usb: usb@a6f8800 { 
			assigned-clock-rates = <19200000>, <200000000>;



			interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,

					      <&pdc 19 IRQ_TYPE_EDGE_BOTH>,

					      <&pdc 76 IRQ_TYPE_LEVEL_HIGH>,

					      <&pdc 18 IRQ_TYPE_EDGE_BOTH>;

			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",

					  "ss_phy_irq", "dm_hs_phy_irq";

					      <&pdc 18 IRQ_TYPE_EDGE_BOTH>,

					      <&pdc 19 IRQ_TYPE_EDGE_BOTH>;

			interrupt-names = "hs_phy_irq",

					  "ss_phy_irq",

					  "dm_hs_phy_irq",

					  "dp_hs_phy_irq";



			power-domains = <&gcc USB30_GDSC>;