Commit 08fdb6f3 authored by Vadim Pasternak's avatar Vadim Pasternak Committed by Hans de Goede
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platform/x86: mlx-platform: Add support for systems equipped with two ASICs 



Motivation is to support new systems equipped with two ASICs.

Extend driver with:
- The second ASIC health event.
- Per ASIC reset control, triggering reset of ASIC internal resources
  and restarting ASIC initialization flow.

Signed-off-by: default avatarVadim Pasternak <vadimp@nvidia.com>
Reviewed-by: default avatarOleksandr Shamray <oleksandrs@nvidia.com>
Link: https://lore.kernel.org/r/20220711084559.62447-4-vadimp@nvidia.com


Reviewed-by: default avatarHans de Goede <hdegoede@redhat.com>
Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
parent 7bf8a14d

drivers/platform/x86/mlx-platform.c

+51 −1
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ 
#define MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET	0x09

#define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET	0x0a

#define MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET	0x0b

#define MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET	0x19

#define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET	0x1c

#define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET	0x1d

#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET	0x1e
@@ -69,6 +70,9 @@ 
#define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50

#define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET	0x51

#define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET	0x52

#define MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET 0x53

#define MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET	0x54

#define MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET	0x55

#define MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET	0x56

#define MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET	0x57

#define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET		0x58
@@ -193,6 +197,7 @@ 
					 MLXPLAT_CPLD_AGGR_MASK_LC_ACT | \

					 MLXPLAT_CPLD_AGGR_MASK_LC_SDWN)

#define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW	0xc1

#define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2	BIT(2)

#define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C	BIT(6)

#define MLXPLAT_CPLD_PSU_MASK		GENMASK(1, 0)

#define MLXPLAT_CPLD_PWR_MASK		GENMASK(1, 0)
@@ -588,6 +593,15 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_asic_items_data[] = { 
	},

};



static struct mlxreg_core_data mlxplat_mlxcpld_default_asic2_items_data[] = {

	{

		.label = "asic2",

		.reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET,

		.mask = MLXPLAT_CPLD_ASIC_MASK,

		.hpdev.nr = MLXPLAT_CPLD_NR_NONE,

	},

};



static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = {

	{

		.data = mlxplat_mlxcpld_default_psu_items_data,
@@ -1151,6 +1165,15 @@ static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = { 
		.inversed = 0,

		.health = true,

	},

	{

		.data = mlxplat_mlxcpld_default_asic2_items_data,

		.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,

		.reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET,

		.mask = MLXPLAT_CPLD_ASIC_MASK,

		.count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic2_items_data),

		.inversed = 0,

		.health = true,

	}

};



static
@@ -1160,7 +1183,7 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { 
	.cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,

	.mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX,

	.cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,

	.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,

	.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2,

};



static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = {
@@ -2856,6 +2879,18 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { 
		.bit = GENMASK(7, 0),

		.mode = 0444,

	},

	{

		.label = "asic_reset",

		.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET,

		.mask = GENMASK(7, 0) & ~BIT(3),

		.mode = 0200,

	},

	{

		.label = "asic2_reset",

		.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET,

		.mask = GENMASK(7, 0) & ~BIT(2),

		.mode = 0200,

	},

	{

		.label = "reset_long_pb",

		.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
@@ -2995,6 +3030,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { 
		.bit = 1,

		.mode = 0444,

	},

	{

		.label = "asic2_health",

		.reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET,

		.mask = MLXPLAT_CPLD_ASIC_MASK,

		.bit = 1,

		.mode = 0444,

	},

	{

		.label = "fan_dir",

		.reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION,
@@ -3934,6 +3976,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) 
	case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET:
@@ -4026,6 +4070,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) 
	case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
@@ -4153,6 +4200,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) 
	case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: