Commit 0959bc4b authored by Yuji Ishikawa's avatar Yuji Ishikawa Committed by David S. Miller
Browse files

net: stmmac: dwmac-visconti: Fix clock configuration for RMII mode 



Bit pattern of the ETHER_CLOCK_SEL register for RMII/MII mode should be fixed.
Also, some control bits should be modified with a specific sequence.

Fixes: b38dd98f ("net: stmmac: Add Toshiba Visconti SoCs glue driver")
Signed-off-by: default avatarYuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
Reviewed-by: default avatarNobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 1ba1a4a9

drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c

+21 −11
Original line number Diff line number Diff line
@@ -96,30 +96,40 @@ static void visconti_eth_fix_mac_speed(void *priv, unsigned int speed) 
	val |= ETHER_CLK_SEL_TX_O_E_N_IN;

	writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);



	/* Set Clock-Mux, Start clock, Set TX_O direction */

	switch (dwmac->phy_intf_sel) {

	case ETHER_CONFIG_INTF_RGMII:

		val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);



		val |= ETHER_CLK_SEL_RX_TX_CLK_EN;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);



		val &= ~ETHER_CLK_SEL_TX_O_E_N_IN;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);

		break;

	case ETHER_CONFIG_INTF_RMII:

		val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_DIV |

			ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC | ETHER_CLK_SEL_TX_O_E_N_IN |

			ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV | ETHER_CLK_SEL_TX_O_E_N_IN |

			ETHER_CLK_SEL_RMII_CLK_SEL_RX_C;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);



		val |= ETHER_CLK_SEL_RMII_CLK_RST;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);



		val |= ETHER_CLK_SEL_RMII_CLK_EN | ETHER_CLK_SEL_RX_TX_CLK_EN;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);

		break;

	case ETHER_CONFIG_INTF_MII:

	default:

		val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC |

			ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV | ETHER_CLK_SEL_TX_O_E_N_IN |

			ETHER_CLK_SEL_RMII_CLK_EN;

		break;

	}



	/* Start clock */

	writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);

	val |= ETHER_CLK_SEL_RX_TX_CLK_EN;

			ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC | ETHER_CLK_SEL_TX_O_E_N_IN;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);



	val &= ~ETHER_CLK_SEL_TX_O_E_N_IN;

		val |= ETHER_CLK_SEL_RX_TX_CLK_EN;

		writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);

		break;

	}



	spin_unlock_irqrestore(&dwmac->lock, flags);

}