Commit 095a2c18 authored by Vadim Pasternak's avatar Vadim Pasternak Committed by Hans de Goede
Browse files

platform/x86: mlx-platform: Add COME board revision register 



Extend COME CPLD with board configuration register for getting board
revision. The value of this register is pushed by hardware through GPIO
pins.
The purpose of it is to expose some minor BOM changes.

Signed-off-by: default avatarVadim Pasternak <vadimp@nvidia.com>
Reviewed-by: default avatarOleksandr Shamray <oleksandrs@nvidia.com>
Link: https://lore.kernel.org/r/20220711084559.62447-7-vadimp@nvidia.com


Reviewed-by: default avatarHans de Goede <hdegoede@redhat.com>
Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
parent 2deb9286

drivers/platform/x86/mlx-platform.c

+21 −0
Original line number Diff line number Diff line
@@ -150,6 +150,7 @@ 
#define MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET	0xfa

#define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET	0xfb

#define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET	0xfc

#define MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET	0xfd

#define MLXPLAT_CPLD_LPC_IO_RANGE		0x100

#define MLXPLAT_CPLD_LPC_I2C_CH1_OFF		0xdb

#define MLXPLAT_CPLD_LPC_I2C_CH2_OFF		0xda
@@ -3153,6 +3154,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { 
		.bit = GENMASK(7, 0),

		.mode = 0444,

	},

	{

		.label = "config3",

		.reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET,

		.bit = GENMASK(7, 0),

		.mode = 0444,

	},

	{

		.label = "ufm_version",

		.reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET,
@@ -3631,6 +3638,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = { 
		.bit = GENMASK(7, 0),

		.mode = 0444,

	},

	{

		.label = "config3",

		.reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET,

		.bit = GENMASK(7, 0),

		.mode = 0444,

	},

	{

		.label = "ufm_version",

		.reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET,
@@ -3828,6 +3841,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_nvlink_blade_regs_io_data[] = { 
		.bit = GENMASK(7, 0),

		.mode = 0444,

	},

	{

		.label = "config3",

		.reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET,

		.bit = GENMASK(7, 0),

		.mode = 0444,

	},

	{

		.label = "ufm_version",

		.reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET,
@@ -4404,6 +4423,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) 
	case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET:

		return true;

	}
@@ -4531,6 +4551,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) 
	case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET:

	case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET:

		return true;

	}