Commit 0a4499df authored by Alexandre Belloni's avatar Alexandre Belloni
Browse files

ARM: dts: at91: at91sam9rl: switch to new clock bindings 



Switch at91sam9rl boards to the new PMC clock bindings.

Signed-off-by: default avatarAlexandre Belloni <alexandre.belloni@bootlin.com>
parent 6cf8f828

arch/arm/boot/dts/at91sam9rl.dtsi

+23 −216
Original line number Diff line number Diff line
@@ -88,7 +88,7 @@ fb0: fb@500000 { 
			interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_fb>;

			clocks = <&lcd_clk>, <&lcd_clk>;

			clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>;

			clock-names = "hclk", "lcdc_clk";

			status = "disabled";

		};
@@ -106,7 +106,7 @@ ebi: ebi@10000000 { 
				  0x3 0x0 0x40000000 0x10000000

				  0x4 0x0 0x50000000 0x10000000

				  0x5 0x0 0x60000000 0x10000000>;

			clocks = <&mck>;

			clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;

			status = "disabled";



			nand_controller: nand-controller {
@@ -132,7 +132,7 @@ tcb0: timer@fffa0000 { 
				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>,

					     <17 IRQ_TYPE_LEVEL_HIGH 0>,

					     <18 IRQ_TYPE_LEVEL_HIGH 0>;

				clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;

				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>, <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>;

				clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";

			};
@@ -143,7 +143,7 @@ mmc0: mmc@fffa4000 { 
				#address-cells = <1>;

				#size-cells = <0>;

				pinctrl-names = "default";

				clocks = <&mci0_clk>;

				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;

				clock-names = "mci_clk";

				status = "disabled";

			};
@@ -154,7 +154,7 @@ i2c0: i2c@fffa8000 { 
				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;

				#address-cells = <1>;

				#size-cells = <0>;

				clocks = <&twi0_clk>;

				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;

				status = "disabled";

			};
@@ -175,7 +175,7 @@ usart0: serial@fffb0000 { 
				atmel,use-dma-tx;

				pinctrl-names = "default";

				pinctrl-0 = <&pinctrl_usart0>;

				clocks = <&usart0_clk>;

				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;

				clock-names = "usart";

				status = "disabled";

			};
@@ -188,7 +188,7 @@ usart1: serial@fffb4000 { 
				atmel,use-dma-tx;

				pinctrl-names = "default";

				pinctrl-0 = <&pinctrl_usart1>;

				clocks = <&usart1_clk>;

				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;

				clock-names = "usart";

				status = "disabled";

			};
@@ -201,7 +201,7 @@ usart2: serial@fffb8000 { 
				atmel,use-dma-tx;

				pinctrl-names = "default";

				pinctrl-0 = <&pinctrl_usart2>;

				clocks = <&usart2_clk>;

				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;

				clock-names = "usart";

				status = "disabled";

			};
@@ -214,7 +214,7 @@ usart3: serial@fffbc000 { 
				atmel,use-dma-tx;

				pinctrl-names = "default";

				pinctrl-0 = <&pinctrl_usart3>;

				clocks = <&usart3_clk>;

				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;

				clock-names = "usart";

				status = "disabled";

			};
@@ -242,7 +242,7 @@ pwm0: pwm@fffc8000 { 
				reg = <0xfffc8000 0x300>;

				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;

				#pwm-cells = <3>;

				clocks = <&pwm_clk>;

				clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;

				clock-names = "pwm_clk";

				status = "disabled";

			};
@@ -255,7 +255,7 @@ spi0: spi@fffcc000 { 
				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;

				pinctrl-names = "default";

				pinctrl-0 = <&pinctrl_spi0>;

				clocks = <&spi0_clk>;

				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;

				clock-names = "spi_clk";

				status = "disabled";

			};
@@ -266,7 +266,7 @@ adc0: adc@fffd0000 { 
				compatible = "atmel,at91sam9rl-adc";

				reg = <0xfffd0000 0x100>;

				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;

				clocks = <&adc_clk>, <&adc_op_clk>;

				clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&adc_op_clk>;

				clock-names = "adc_clk", "adc_op_clk";

				atmel,adc-use-external-triggers;

				atmel,adc-channels-used = <0x3f>;
@@ -304,7 +304,7 @@ usb0: gadget@fffd4000 { 
				reg = <0x00600000 0x100000>,

				      <0xfffd4000 0x4000>;

				interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;

				clocks = <&udphs_clk>, <&utmi>;

				clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_CORE PMC_UTMI>;

				clock-names = "pclk", "hclk";

				status = "disabled";
@@ -366,7 +366,7 @@ dma0: dma-controller@ffffe600 { 
				reg = <0xffffe600 0x200>;

				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;

				#dma-cells = <2>;

				clocks = <&dma0_clk>;

				clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;

				clock-names = "dma_clk";

			};
@@ -399,7 +399,7 @@ dbgu: serial@fffff200 { 
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;

				pinctrl-names = "default";

				pinctrl-0 = <&pinctrl_dbgu>;

				clocks = <&mck>;

				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;

				clock-names = "usart";

				status = "disabled";

			};
@@ -794,7 +794,7 @@ pioA: gpio@fffff400 { 
					gpio-controller;

					interrupt-controller;

					#interrupt-cells = <2>;

					clocks = <&pioA_clk>;

					clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;

				};



				pioB: gpio@fffff600 {
@@ -805,7 +805,7 @@ pioB: gpio@fffff600 { 
					gpio-controller;

					interrupt-controller;

					#interrupt-cells = <2>;

					clocks = <&pioB_clk>;

					clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;

				};



				pioC: gpio@fffff800 {
@@ -816,7 +816,7 @@ pioC: gpio@fffff800 { 
					gpio-controller;

					interrupt-controller;

					#interrupt-cells = <2>;

					clocks = <&pioC_clk>;

					clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;

				};



				pioD: gpio@fffffa00 {
@@ -827,7 +827,7 @@ pioD: gpio@fffffa00 { 
					gpio-controller;

					interrupt-controller;

					#interrupt-cells = <2>;

					clocks = <&pioD_clk>;

					clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;

				};

			};
@@ -835,202 +835,9 @@ pmc: pmc@fffffc00 { 
				compatible = "atmel,at91sam9rl-pmc", "syscon";

				reg = <0xfffffc00 0x100>;

				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;

				interrupt-controller;

				#address-cells = <1>;

				#size-cells = <0>;

				#interrupt-cells = <1>;



				main: mainck {

					compatible = "atmel,at91rm9200-clk-main";

					#clock-cells = <0>;

					interrupts-extended = <&pmc AT91_PMC_MOSCS>;

					clocks = <&main_xtal>;

				};



				plla: pllack {

					compatible = "atmel,at91rm9200-clk-pll";

					#clock-cells = <0>;

					interrupts-extended = <&pmc AT91_PMC_LOCKA>;

					clocks = <&main>;

					reg = <0>;

					atmel,clk-input-range = <1000000 32000000>;

					#atmel,pll-clk-output-range-cells = <3>;

					atmel,pll-clk-output-ranges = <80000000 200000000 0>,

								<190000000 240000000 2>;

				};



				utmi: utmick {

					compatible = "atmel,at91sam9x5-clk-utmi";

					#clock-cells = <0>;

					interrupt-parent = <&pmc>;

					interrupts = <AT91_PMC_LOCKU>;

					clocks = <&main>;

				};



				mck: masterck {

					compatible = "atmel,at91rm9200-clk-master";

					#clock-cells = <0>;

					interrupts-extended = <&pmc AT91_PMC_MCKRDY>;

					clocks = <&clk32k>, <&main>, <&plla>, <&utmi>;

					atmel,clk-output-range = <0 94000000>;

					atmel,clk-divisors = <1 2 4 0>;

				};



				prog: progck {

					compatible = "atmel,at91rm9200-clk-programmable";

					#address-cells = <1>;

					#size-cells = <0>;

					interrupt-parent = <&pmc>;

					clocks = <&clk32k>, <&main>, <&plla>, <&utmi>, <&mck>;



					prog0: prog0 {

						#clock-cells = <0>;

						reg = <0>;

						interrupts = <AT91_PMC_PCKRDY(0)>;

					};



					prog1: prog1 {

						#clock-cells = <0>;

						reg = <1>;

						interrupts = <AT91_PMC_PCKRDY(1)>;

					};

				};



				systemck {

					compatible = "atmel,at91rm9200-clk-system";

					#address-cells = <1>;

					#size-cells = <0>;



					pck0: pck0 {

						#clock-cells = <0>;

						reg = <8>;

						clocks = <&prog0>;

					};



					pck1: pck1 {

						#clock-cells = <0>;

						reg = <9>;

						clocks = <&prog1>;

					};



				};



				periphck {

					compatible = "atmel,at91rm9200-clk-peripheral";

					#address-cells = <1>;

					#size-cells = <0>;

					clocks = <&mck>;



					pioA_clk: pioA_clk {

						#clock-cells = <0>;

						reg = <2>;

					};



					pioB_clk: pioB_clk {

						#clock-cells = <0>;

						reg = <3>;

					};



					pioC_clk: pioC_clk {

						#clock-cells = <0>;

						reg = <4>;

					};



					pioD_clk: pioD_clk {

						#clock-cells = <0>;

						reg = <5>;

					};



					usart0_clk: usart0_clk {

						#clock-cells = <0>;

						reg = <6>;

					};



					usart1_clk: usart1_clk {

						#clock-cells = <0>;

						reg = <7>;

					};



					usart2_clk: usart2_clk {

						#clock-cells = <0>;

						reg = <8>;

					};



					usart3_clk: usart3_clk {

						#clock-cells = <0>;

						reg = <9>;

					};



					mci0_clk: mci0_clk {

						#clock-cells = <0>;

						reg = <10>;

					};



					twi0_clk: twi0_clk {

						#clock-cells = <0>;

						reg = <11>;

					};



					twi1_clk: twi1_clk {

						#clock-cells = <0>;

						reg = <12>;

					};



					spi0_clk: spi0_clk {

						#clock-cells = <0>;

						reg = <13>;

					};



					ssc0_clk: ssc0_clk {

						#clock-cells = <0>;

						reg = <14>;

					};



					ssc1_clk: ssc1_clk {

						#clock-cells = <0>;

						reg = <15>;

					};



					tc0_clk: tc0_clk {

						#clock-cells = <0>;

						reg = <16>;

					};



					tc1_clk: tc1_clk {

						#clock-cells = <0>;

						reg = <17>;

					};



					tc2_clk: tc2_clk {

						#clock-cells = <0>;

						reg = <18>;

					};



					pwm_clk: pwm_clk {

						#clock-cells = <0>;

						reg = <19>;

					};



					adc_clk: adc_clk {

						#clock-cells = <0>;

						reg = <20>;

					};



					dma0_clk: dma0_clk {

						#clock-cells = <0>;

						reg = <21>;

					};



					udphs_clk: udphs_clk {

						#clock-cells = <0>;

						reg = <22>;

					};



					lcd_clk: lcd_clk {

						#clock-cells = <0>;

						reg = <23>;

					};

				};

				#clock-cells = <2>;

				clocks = <&clk32k>, <&main_xtal>;

				clock-names = "slow_clk", "main_xtal";

			};



			rstc@fffffd00 {
@@ -1049,7 +856,7 @@ pit: timer@fffffd30 { 
				compatible = "atmel,at91sam9260-pit";

				reg = <0xfffffd30 0xf>;

				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;

				clocks = <&mck>;

				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;

			};



			watchdog@fffffd40 {