Commit 0a83bb35 authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amdgpu: Avoid another list of reset devices 



A list of devices to be reset is already created in
amdgpu_device_gpu_recover function. Creating another list with the
same nodes is incorrect and not supported in list_head. Instead, pass
the device list as part of reset context.

Fixes: 9e085647 (drm/amdgpu: Refactor mode2 reset logic for v13.0.2)
Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b2f6c735

drivers/gpu/drm/amd/amdgpu/aldebaran.c

+14 −31
Original line number Diff line number Diff line
@@ -148,30 +148,22 @@ aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl, 
			      struct amdgpu_reset_context *reset_context)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;

	struct list_head *reset_device_list = reset_context->reset_device_list;

	struct amdgpu_device *tmp_adev = NULL;

	struct list_head reset_device_list;

	int r = 0;



	dev_dbg(adev->dev, "aldebaran perform hw reset\n");



	if (reset_device_list == NULL)

		return -EINVAL;



	if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) &&

	    reset_context->hive == NULL) {

		/* Wrong context, return error */

		return -EINVAL;

	}



	INIT_LIST_HEAD(&reset_device_list);

	if (reset_context->hive) {

		list_for_each_entry (tmp_adev,

				     &reset_context->hive->device_list,

				     gmc.xgmi.head)

			list_add_tail(&tmp_adev->reset_list,

				      &reset_device_list);

	} else {

		list_add_tail(&reset_context->reset_req_dev->reset_list,

			      &reset_device_list);

	}



	list_for_each_entry (tmp_adev, &reset_device_list, reset_list) {

	list_for_each_entry(tmp_adev, reset_device_list, reset_list) {

		mutex_lock(&tmp_adev->reset_cntl->reset_lock);

		tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_MODE2;

	}
@@ -179,7 +171,7 @@ aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl, 
	 * Mode2 reset doesn't need any sync between nodes in XGMI hive, instead launch

	 * them together so that they can be completed asynchronously on multiple nodes

	 */

	list_for_each_entry (tmp_adev, &reset_device_list, reset_list) {

	list_for_each_entry(tmp_adev, reset_device_list, reset_list) {

		/* For XGMI run all resets in parallel to speed up the process */

		if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {

			if (!queue_work(system_unbound_wq,
@@ -197,7 +189,7 @@ aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl, 


	/* For XGMI wait for all resets to complete before proceed */

	if (!r) {

		list_for_each_entry (tmp_adev, &reset_device_list, reset_list) {

		list_for_each_entry(tmp_adev, reset_device_list, reset_list) {

			if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {

				flush_work(&tmp_adev->reset_cntl->reset_work);

				r = tmp_adev->asic_reset_res;
@@ -207,7 +199,7 @@ aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl, 
		}

	}



	list_for_each_entry (tmp_adev, &reset_device_list, reset_list) {

	list_for_each_entry(tmp_adev, reset_device_list, reset_list) {

		mutex_unlock(&tmp_adev->reset_cntl->reset_lock);

		tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_NONE;

	}
@@ -339,10 +331,13 @@ static int 
aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,

				  struct amdgpu_reset_context *reset_context)

{

	struct list_head *reset_device_list = reset_context->reset_device_list;

	struct amdgpu_device *tmp_adev = NULL;

	struct list_head reset_device_list;

	int r;



	if (reset_device_list == NULL)

		return -EINVAL;



	if (reset_context->reset_req_dev->ip_versions[MP1_HWIP][0] ==

		    IP_VERSION(13, 0, 2) &&

	    reset_context->hive == NULL) {
@@ -350,19 +345,7 @@ aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl, 
		return -EINVAL;

	}



	INIT_LIST_HEAD(&reset_device_list);

	if (reset_context->hive) {

		list_for_each_entry (tmp_adev,

				     &reset_context->hive->device_list,

				     gmc.xgmi.head)

			list_add_tail(&tmp_adev->reset_list,

				      &reset_device_list);

	} else {

		list_add_tail(&reset_context->reset_req_dev->reset_list,

			      &reset_device_list);

	}



	list_for_each_entry (tmp_adev, &reset_device_list, reset_list) {

	list_for_each_entry(tmp_adev, reset_device_list, reset_list) {

		dev_info(tmp_adev->dev,

			 "GPU reset succeeded, trying to resume\n");

		r = aldebaran_mode2_restore_ip(tmp_adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+2 −0
Original line number Diff line number Diff line
@@ -4742,6 +4742,8 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, 
	tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,

				    reset_list);

	amdgpu_reset_reg_dumps(tmp_adev);



	reset_context->reset_device_list = device_list_handle;

	r = amdgpu_reset_perform_reset(tmp_adev, reset_context);

	/* If reset handler not implemented, continue; otherwise return */

	if (r == -ENOSYS)

drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h

+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ struct amdgpu_reset_context { 
	struct amdgpu_device *reset_req_dev;

	struct amdgpu_job *job;

	struct amdgpu_hive_info *hive;

	struct list_head *reset_device_list;

	unsigned long flags;

};