Commit 0a8c91d7 authored by Hamza Mahfooz's avatar Hamza Mahfooz Committed by Alex Deucher
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drm/amd/display: include soc._clock_tmp[] into DC's scratch region 



Currently, we are using soc._clock_tmp[] to temporarily store and modify
data from soc.clock_limits[] before copying it back into
soc.clock_limits[] (because modifying data directly in
soc.clock_limits[] causes unintended behavior). However, this approach
has a number of downsides, such as:

	1. struct _vcs_dpi_soc_bounding_box_st's creation/destruction
	   aren't well defined (which could mean more unintended
	   behavior).
	2. Throwing "temp" varibles in structs everywhere doesn't make
	   for a particularly readable codebase.

For these reasons, we should get rid of soc._clock_tmp[] by defining a
struct scratch within struct dc that, contains within it all of the
temporary variables (including _clock_tmp[]) such that it is obvious how
they are intended to be used.

Co-authored-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a4d32303

drivers/gpu/drm/amd/display/dc/dc.h

+11 −0
Original line number Diff line number Diff line
@@ -900,6 +900,17 @@ struct dc { 


	uint32_t *dcn_reg_offsets;

	uint32_t *nbio_reg_offsets;



	/* Scratch memory */

	struct {

		struct {

			/*

			 * For matching clock_limits table in driver with table

			 * from PMFW.

			 */

			struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];

		} update_bw_bounding_box;

	} scratch;

};



enum frame_buffer_mode {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

+17 −17
Original line number Diff line number Diff line
@@ -2234,6 +2234,7 @@ static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_li 


void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

{

	struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;

	struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);

	struct clk_limit_table *clk_table = &bw_params->clk_table;

	unsigned int i, closest_clk_lvl = 0, k = 0;
@@ -2247,8 +2248,7 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params 


	ASSERT(clk_table->num_entries);

	/* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */

	memcpy(&dcn2_1_soc._clock_tmp, &dcn2_1_soc.clock_limits,

	       sizeof(dcn2_1_soc.clock_limits));

	memcpy(s, dcn2_1_soc.clock_limits, sizeof(dcn2_1_soc.clock_limits));



	for (i = 0; i < clk_table->num_entries; i++) {

		/* loop backwards*/
@@ -2263,25 +2263,25 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params 
		if (i == 1)

			k++;



		dcn2_1_soc._clock_tmp[k].state = k;

		dcn2_1_soc._clock_tmp[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;

		dcn2_1_soc._clock_tmp[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;

		dcn2_1_soc._clock_tmp[k].socclk_mhz = clk_table->entries[i].socclk_mhz;

		dcn2_1_soc._clock_tmp[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;



		dcn2_1_soc._clock_tmp[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;

		dcn2_1_soc._clock_tmp[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;

		dcn2_1_soc._clock_tmp[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;

		dcn2_1_soc._clock_tmp[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;

		dcn2_1_soc._clock_tmp[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;

		dcn2_1_soc._clock_tmp[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;

		dcn2_1_soc._clock_tmp[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;

		s[k].state = k;

		s[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;

		s[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;

		s[k].socclk_mhz = clk_table->entries[i].socclk_mhz;

		s[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;



		s[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;

		s[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;

		s[k].dram_bw_per_chan_gbps =

			dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;

		s[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;

		s[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;

		s[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;

		s[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;



		k++;

	}



	memcpy(&dcn2_1_soc.clock_limits, &dcn2_1_soc._clock_tmp,

	       sizeof(dcn2_1_soc.clock_limits));

	memcpy(dcn2_1_soc.clock_limits, s, sizeof(dcn2_1_soc.clock_limits));



	if (clk_table->num_entries) {

		dcn2_1_soc.num_states = clk_table->num_entries + 1;

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

+21 −19
Original line number Diff line number Diff line
@@ -322,6 +322,7 @@ static void calculate_wm_set_for_vlevel(int vlevel, 


void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

{

	struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;

	struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool);

	struct clk_limit_table *clk_table = &bw_params->clk_table;

	unsigned int i, closest_clk_lvl;
@@ -329,8 +330,7 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param 


	dc_assert_fp_enabled();



	memcpy(&dcn3_01_soc._clock_tmp, &dcn3_01_soc.clock_limits,

	       sizeof(dcn3_01_soc.clock_limits));

	memcpy(s, dcn3_01_soc.clock_limits, sizeof(dcn3_01_soc.clock_limits));



	/* Default clock levels are used for diags, which may lead to overclocking. */

	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
@@ -348,31 +348,33 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param 
				}

			}



			dcn3_01_soc._clock_tmp[i].state = i;

			dcn3_01_soc._clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;

			dcn3_01_soc._clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;

			dcn3_01_soc._clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz;

			dcn3_01_soc._clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;



			dcn3_01_soc._clock_tmp[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz;

			dcn3_01_soc._clock_tmp[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz;

			dcn3_01_soc._clock_tmp[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;

			dcn3_01_soc._clock_tmp[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz;

			dcn3_01_soc._clock_tmp[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;

			dcn3_01_soc._clock_tmp[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;

			dcn3_01_soc._clock_tmp[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz;

			s[i].state = i;

			s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;

			s[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;

			s[i].socclk_mhz = clk_table->entries[i].socclk_mhz;

			s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;



			s[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz;

			s[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz;

			s[i].dram_bw_per_chan_gbps =

				dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;

			s[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz;

			s[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;

			s[i].phyclk_d18_mhz =

				dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;

			s[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz;

		}



		if (clk_table->num_entries) {

			dcn3_01_soc.num_states = clk_table->num_entries;

			/* duplicate last level */

			dcn3_01_soc._clock_tmp[dcn3_01_soc.num_states] = dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1];

			dcn3_01_soc._clock_tmp[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states;

			s[dcn3_01_soc.num_states] =

				dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1];

			s[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states;

		}

	}



	memcpy(&dcn3_01_soc.clock_limits, &dcn3_01_soc._clock_tmp,

	       sizeof(dcn3_01_soc.clock_limits));

	memcpy(dcn3_01_soc.clock_limits, s, sizeof(dcn3_01_soc.clock_limits));



	dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

+42 −35
Original line number Diff line number Diff line
@@ -597,14 +597,14 @@ void dcn31_calculate_wm_and_dlg_fp( 


void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

{

	struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;

	struct clk_limit_table *clk_table = &bw_params->clk_table;

	unsigned int i, closest_clk_lvl;

	int j;



	dc_assert_fp_enabled();



	memcpy(&dcn3_1_soc._clock_tmp, &dcn3_1_soc.clock_limits,

	       sizeof(dcn3_1_soc.clock_limits));

	memcpy(s, dcn3_1_soc.clock_limits, sizeof(dcn3_1_soc.clock_limits));



	// Default clock levels are used for diags, which may lead to overclocking.

	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
@@ -633,34 +633,36 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params 
				}

			}



			dcn3_1_soc._clock_tmp[i].state = i;

			s[i].state = i;



			/* Clocks dependent on voltage level. */

			dcn3_1_soc._clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;

			dcn3_1_soc._clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;

			dcn3_1_soc._clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz;

			dcn3_1_soc._clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;

			s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;

			s[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;

			s[i].socclk_mhz = clk_table->entries[i].socclk_mhz;

			s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz *

				2 * clk_table->entries[i].wck_ratio;



			/* Clocks independent of voltage level. */

			dcn3_1_soc._clock_tmp[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :

			s[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :

				dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;



			dcn3_1_soc._clock_tmp[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :

			s[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :

				dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;



			dcn3_1_soc._clock_tmp[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;

			dcn3_1_soc._clock_tmp[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;

			dcn3_1_soc._clock_tmp[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;

			dcn3_1_soc._clock_tmp[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;

			dcn3_1_soc._clock_tmp[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;

			s[i].dram_bw_per_chan_gbps =

				dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;

			s[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;

			s[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;

			s[i].phyclk_d18_mhz =

				dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;

			s[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;

		}

		if (clk_table->num_entries) {

			dcn3_1_soc.num_states = clk_table->num_entries;

		}

	}



	memcpy(&dcn3_1_soc.clock_limits, &dcn3_1_soc._clock_tmp,

	       sizeof(dcn3_1_soc.clock_limits));

	memcpy(dcn3_1_soc.clock_limits, s, sizeof(dcn3_1_soc.clock_limits));



	dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
@@ -727,6 +729,7 @@ void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param 


void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

{

	struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits;

	struct clk_limit_table *clk_table = &bw_params->clk_table;

	unsigned int i, closest_clk_lvl;

	int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
@@ -734,8 +737,7 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param 


	dc_assert_fp_enabled();



	memcpy(&dcn3_16_soc._clock_tmp, &dcn3_16_soc.clock_limits,

	       sizeof(dcn3_16_soc.clock_limits));

	memcpy(s, dcn3_16_soc.clock_limits, sizeof(dcn3_16_soc.clock_limits));



	// Default clock levels are used for diags, which may lead to overclocking.

	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
@@ -757,7 +759,8 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param 
		for (i = 0; i < clk_table->num_entries; i++) {

			/* loop backwards*/

			for (closest_clk_lvl = 0, j = dcn3_16_soc.num_states - 1; j >= 0; j--) {

				if ((unsigned int) dcn3_16_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {

				if ((unsigned int) dcn3_16_soc.clock_limits[j].dcfclk_mhz <=

				    clk_table->entries[i].dcfclk_mhz) {

					closest_clk_lvl = j;

					break;

				}
@@ -768,39 +771,43 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param 
				closest_clk_lvl = dcn3_16_soc.num_states - 1;

			}



			dcn3_16_soc._clock_tmp[i].state = i;

			s[i].state = i;



			/* Clocks dependent on voltage level. */

			dcn3_16_soc._clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;

			s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;

			if (clk_table->num_entries == 1 &&

			    dcn3_16_soc._clock_tmp[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {

			    s[i].dcfclk_mhz <

			    dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {

				/*SMU fix not released yet*/

				dcn3_16_soc._clock_tmp[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;

				s[i].dcfclk_mhz =

					dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;

			}

			dcn3_16_soc._clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;

			dcn3_16_soc._clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz;

			dcn3_16_soc._clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;

			s[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;

			s[i].socclk_mhz = clk_table->entries[i].socclk_mhz;

			s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz *

				2 * clk_table->entries[i].wck_ratio;



			/* Clocks independent of voltage level. */

			dcn3_16_soc._clock_tmp[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :

			s[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :

				dcn3_16_soc.clock_limits[closest_clk_lvl].dispclk_mhz;



			dcn3_16_soc._clock_tmp[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :

			s[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :

				dcn3_16_soc.clock_limits[closest_clk_lvl].dppclk_mhz;



			dcn3_16_soc._clock_tmp[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;

			dcn3_16_soc._clock_tmp[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz;

			dcn3_16_soc._clock_tmp[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;

			dcn3_16_soc._clock_tmp[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;

			dcn3_16_soc._clock_tmp[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz;

			s[i].dram_bw_per_chan_gbps =

				dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;

			s[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz;

			s[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;

			s[i].phyclk_d18_mhz =

				dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;

			s[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz;

		}

		if (clk_table->num_entries) {

			dcn3_16_soc.num_states = clk_table->num_entries;

		}

	}



	memcpy(&dcn3_16_soc.clock_limits, &dcn3_16_soc._clock_tmp,

	       sizeof(dcn3_16_soc.clock_limits));

	memcpy(dcn3_16_soc.clock_limits, s, sizeof(dcn3_16_soc.clock_limits));



	if (max_dispclk_mhz) {

		dcn3_16_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;

drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h

+0 −6
Original line number Diff line number Diff line
@@ -179,12 +179,6 @@ struct _vcs_dpi_voltage_scaling_st { 
 */

struct _vcs_dpi_soc_bounding_box_st {

	struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];

	/*

	 * This is a temporary stash for updating @clock_limits with the PMFW

	 * clock table. Do not use outside of *update_bw_boudning_box functions.

	 */

	struct _vcs_dpi_voltage_scaling_st _clock_tmp[DC__VOLTAGE_STATES];



	/**

	 * @num_states: It represents the total of Display Power Management

	 * (DPM) supported by the specific ASIC.