Commit 0b7421f0 authored by Aurabindo Pillai's avatar Aurabindo Pillai Committed by Alex Deucher
Browse files

drm/amd/display: Old sequence for HUBP blank 



New proposed sequence for HUBP blanking causes regressions where the
hardware would fail to enter blank which triggers an assert in the new
sequence. This change brings back the old sequence.

Fixes: 985faf2c ("drm/amd/display: New sequence for HUBP blank")
Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarBhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Reviewed-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ea1b8c9b

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+7 −29
Original line number Diff line number Diff line
@@ -2635,7 +2635,7 @@ static void dcn10_update_dchubp_dpp( 
	hws->funcs.update_plane_addr(dc, pipe_ctx);



	if (is_pipe_tree_visible(pipe_ctx))

		dc->hwss.set_hubp_blank(dc, pipe_ctx, false);

		hubp->funcs->set_blank(hubp, false);

}



void dcn10_blank_pixel_data(
@@ -3146,16 +3146,13 @@ void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc) 
	return;

}



static struct pipe_ctx *get_pipe_ctx_by_hubp_inst(struct dc_state *context, int mpcc_inst)

static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)

{

	int i;



	for (i = 0; i < MAX_PIPES; i++) {

		if (context->res_ctx.pipe_ctx[i].plane_res.hubp

				&& context->res_ctx.pipe_ctx[i].plane_res.hubp->inst == mpcc_inst) {

			return &context->res_ctx.pipe_ctx[i];

		}



	for (i = 0; i < res_pool->pipe_count; i++) {

		if (res_pool->hubps[i]->inst == mpcc_inst)

			return res_pool->hubps[i];

	}

	ASSERT(false);

	return NULL;
@@ -3178,23 +3175,11 @@ void dcn10_wait_for_mpcc_disconnect( 


	for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {

		if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {

			struct pipe_ctx *restore_bottom_pipe;

			struct pipe_ctx *restore_top_pipe;

			struct pipe_ctx *inst_pipe_ctx = get_pipe_ctx_by_hubp_inst(dc->current_state, mpcc_inst);

			struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);



			ASSERT(inst_pipe_ctx);

			res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);

			pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;

			/*

			 * Set top and bottom pipes NULL, as we don't want

			 * to blank those pipes when disconnecting from MPCC

			 */

			restore_bottom_pipe = inst_pipe_ctx->bottom_pipe;

			restore_top_pipe = inst_pipe_ctx->top_pipe;

			inst_pipe_ctx->top_pipe = inst_pipe_ctx->bottom_pipe = NULL;

			dc->hwss.set_hubp_blank(dc, inst_pipe_ctx, true);

			inst_pipe_ctx->top_pipe = restore_top_pipe;

			inst_pipe_ctx->bottom_pipe = restore_bottom_pipe;

			hubp->funcs->set_blank(hubp, true);

		}

	}
@@ -3747,10 +3732,3 @@ void dcn10_get_clock(struct dc *dc, 
				dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);



}
 


void dcn10_set_hubp_blank(const struct dc *dc,

				struct pipe_ctx *pipe_ctx,

				bool blank_enable)

{

	pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, blank_enable);

}

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h

+0 −3
Original line number Diff line number Diff line
@@ -204,8 +204,5 @@ void dcn10_wait_for_pending_cleared(struct dc *dc, 
		struct dc_state *context);

void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx);

void dcn10_verify_allow_pstate_change_high(struct dc *dc);

void dcn10_set_hubp_blank(const struct dc *dc,

				struct pipe_ctx *pipe_ctx,

				bool blank_enable);



#endif /* __DC_HWSS_DCN10_H__ */

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c

+0 −1
Original line number Diff line number Diff line
@@ -79,7 +79,6 @@ static const struct hw_sequencer_funcs dcn10_funcs = { 
	.set_backlight_level = dce110_set_backlight_level,

	.set_abm_immediate_disable = dce110_set_abm_immediate_disable,

	.set_pipe = dce110_set_pipe,

	.set_hubp_blank = dcn10_set_hubp_blank,

};



static const struct hwseq_private_funcs dcn10_private_funcs = {

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+11 −2
Original line number Diff line number Diff line
@@ -1576,7 +1576,7 @@ static void dcn20_update_dchubp_dpp( 




	if (pipe_ctx->update_flags.bits.enable)

		dc->hwss.set_hubp_blank(dc, pipe_ctx, false);

		hubp->funcs->set_blank(hubp, false);

}
@@ -1772,10 +1772,19 @@ void dcn20_post_unlock_program_front_end( 


	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

		struct pipe_ctx *mpcc_pipe;



		if (pipe->vtp_locked) {

			dc->hwss.set_hubp_blank(dc, pipe, true);

			dc->hwseq->funcs.wait_for_blank_complete(pipe->stream_res.opp);

			pipe->plane_res.hubp->funcs->set_blank(pipe->plane_res.hubp, true);

			pipe->vtp_locked = false;



			for (mpcc_pipe = pipe->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)

				mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true);



			for (i = 0; i < dc->res_pool->pipe_count; i++)

				if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)

					dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);

		}

	}

	/* WA to apply WM setting*/

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c

+0 −1
Original line number Diff line number Diff line
@@ -94,7 +94,6 @@ static const struct hw_sequencer_funcs dcn20_funcs = { 
	.optimize_timing_for_fsft = dcn20_optimize_timing_for_fsft,

#endif

	.set_disp_pattern_generator = dcn20_set_disp_pattern_generator,

	.set_hubp_blank = dcn10_set_hubp_blank,

};



static const struct hwseq_private_funcs dcn20_private_funcs = {