Commit 0bdebfef authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amdgpu: Program xcp_ctl registers as needed 



XCP_CTL register is expected to be programmed by firmware. Under certain
conditions FW may not have programmed it correctly. As a workaround,
program it when FW has not programmed the right values.

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cef600e1

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

+12 −11
Original line number Diff line number Diff line
@@ -621,7 +621,7 @@ static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 
						int num_xccs_per_xcp)

{

	int ret, i, num_xcc;

	u32 tmp = 0;

	u32 tmp = 0, regval;



	if (adev->psp.funcs) {

		ret = psp_spatial_partition(&adev->psp,
@@ -629,7 +629,8 @@ static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 
						    num_xccs_per_xcp);

		if (ret)

			return ret;

	} else {

	}



	num_xcc = NUM_XCC(adev->gfx.xcc_mask);



	for (i = 0; i < num_xcc; i++) {
@@ -637,15 +638,15 @@ static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 
				    num_xccs_per_xcp);

		tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID,

				    i % num_xccs_per_xcp);

		regval = RREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL);

		if (regval != tmp)

			WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL,

				     tmp);

	}

		ret = 0;

	}



	adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp;



	return ret;

	return 0;

}



static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node)