Commit 0f1a6ad7 authored by Jun Lei's avatar Jun Lei Committed by Alex Deucher
Browse files

drm/amd/display: PPLIB Hookup 



[Why]
Make dml and integration with pplib clearer.

[How]
Change the way the dml formula is initialized to make its values more
clear. Restructure DC interface with pplib into rv_funcs.
Cap clocks received from pplib.

Signed-off-by: default avatarJun Lei <Jun.Lei@amd.com>
Signed-off-by: default avatarEryk Brol <eryk.brol@amd.com>
Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c7b0f712

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

+10 −10
Original line number Diff line number Diff line
@@ -611,17 +611,17 @@ void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz) 
	pp_funcs->set_hard_min_fclk_by_freq(pp_handle, mhz);

}



void dm_pp_get_funcs_rv(

void dm_pp_get_funcs(

		struct dc_context *ctx,

		struct pp_smu_funcs_rv *funcs)

		struct pp_smu_funcs *funcs)

{

	funcs->pp_smu.dm = ctx;

	funcs->set_display_requirement = pp_rv_set_display_requirement;

	funcs->set_wm_ranges = pp_rv_set_wm_ranges;

	funcs->set_pme_wa_enable = pp_rv_set_pme_wa_enable;

	funcs->set_display_count = pp_rv_set_active_display_count;

	funcs->set_min_deep_sleep_dcfclk = pp_rv_set_min_deep_sleep_dcfclk;

	funcs->set_hard_min_dcfclk_by_freq = pp_rv_set_hard_min_dcefclk_by_freq;

	funcs->set_hard_min_fclk_by_freq = pp_rv_set_hard_min_fclk_by_freq;

	funcs->rv_funcs.pp_smu.dm = ctx;

	funcs->rv_funcs.set_display_requirement = pp_rv_set_display_requirement;

	funcs->rv_funcs.set_wm_ranges = pp_rv_set_wm_ranges;

	funcs->rv_funcs.set_pme_wa_enable = pp_rv_set_pme_wa_enable;

	funcs->rv_funcs.set_display_count = pp_rv_set_active_display_count;

	funcs->rv_funcs.set_min_deep_sleep_dcfclk = pp_rv_set_min_deep_sleep_dcfclk;

	funcs->rv_funcs.set_hard_min_dcfclk_by_freq = pp_rv_set_hard_min_dcefclk_by_freq;

	funcs->rv_funcs.set_hard_min_fclk_by_freq = pp_rv_set_hard_min_fclk_by_freq;

}

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

+1 −1
Original line number Diff line number Diff line
@@ -1391,7 +1391,7 @@ void dcn_bw_update_from_pplib(struct dc *dc) 


void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)

{

	struct pp_smu_funcs_rv *pp = dc->res_pool->pp_smu;

	struct pp_smu_funcs_rv *pp = &dc->res_pool->pp_smu->rv_funcs;

	struct pp_smu_wm_range_sets ranges = {0};

	int min_fclk_khz, min_dcfclk_khz, socclk_khz;

	const int overdrive = 5000000; /* 5 GHz to cover Overdrive */

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+28 −9
Original line number Diff line number Diff line
@@ -935,13 +935,31 @@ void hwss_edp_backlight_control( 
		edp_receiver_ready_T9(link);

}



// Static helper function which calls the correct function

// based on pp_smu version

static void set_pme_wa_enable_by_version(struct dc *dc)

{

	struct pp_smu_funcs *pp_smu = NULL;



	if (dc->res_pool->pp_smu)

		pp_smu = dc->res_pool->pp_smu;



	if (pp_smu) {

		if (pp_smu->ctx.ver == PP_SMU_VER_RV && pp_smu->rv_funcs.set_pme_wa_enable)

			pp_smu->rv_funcs.set_pme_wa_enable(&(pp_smu->ctx));

	}

}



void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)

{

	struct dc *core_dc = pipe_ctx->stream->ctx->dc;

	/* notify audio driver for audio modes of monitor */

	struct pp_smu_funcs_rv *pp_smu = core_dc->res_pool->pp_smu;

	struct dc *core_dc = pipe_ctx->stream->ctx->dc;

	struct pp_smu_funcs *pp_smu = NULL;

	unsigned int i, num_audio = 1;



	if (core_dc->res_pool->pp_smu)

		pp_smu = core_dc->res_pool->pp_smu;



	if (pipe_ctx->stream_res.audio) {

		for (i = 0; i < MAX_PIPES; i++) {

			/*current_state not updated yet*/
@@ -951,9 +969,9 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) 


		pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);



		if (num_audio >= 1 && pp_smu != NULL && pp_smu->set_pme_wa_enable != NULL)

		if (num_audio >= 1 && pp_smu != NULL)

			/*this is the first audio. apply the PME w/a in order to wake AZ from D3*/

			pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);

			set_pme_wa_enable_by_version(core_dc);

		/* un-mute audio */

		/* TODO: audio should be per stream rather than per link */

		pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
@@ -964,17 +982,18 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) 
void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)

{

	struct dc *dc = pipe_ctx->stream->ctx->dc;

	struct pp_smu_funcs *pp_smu = NULL;



	pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(

			pipe_ctx->stream_res.stream_enc, true);

	if (pipe_ctx->stream_res.audio) {

		struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;

		if (dc->res_pool->pp_smu)

			pp_smu = dc->res_pool->pp_smu;



		if (option != KEEP_ACQUIRED_RESOURCE ||

				!dc->debug.az_endpoint_mute_only) {

				!dc->debug.az_endpoint_mute_only)

			/*only disalbe az_endpoint if power down or free*/

			pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);

		}



		if (dc_is_dp_signal(pipe_ctx->stream->signal))

			pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
@@ -989,9 +1008,9 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option) 
			update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);

			pipe_ctx->stream_res.audio = NULL;

		}

		if (pp_smu != NULL && pp_smu->set_pme_wa_enable != NULL)

		if (pp_smu != NULL)

			/*this is the first audio. apply the PME w/a in order to wake AZ from D3*/

			pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);

			set_pme_wa_enable_by_version(dc);



		/* TODO: notify audio driver for if audio modes list changed

		 * add audio mode list change flag */

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c

+1 −1
Original line number Diff line number Diff line
@@ -171,7 +171,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr, 
	struct pp_smu_display_requirement_rv *smu_req_cur =

			&dc->res_pool->pp_smu_req;

	struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;

	struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;

	struct pp_smu_funcs_rv *pp_smu = &dc->res_pool->pp_smu->rv_funcs;

	bool send_request_to_increase = false;

	bool send_request_to_lower = false;

	int display_count;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

+3 −3
Original line number Diff line number Diff line
@@ -848,14 +848,14 @@ void dcn10_clock_source_destroy(struct clock_source **clk_src) 
	*clk_src = NULL;

}



static struct pp_smu_funcs_rv *dcn10_pp_smu_create(struct dc_context *ctx)

static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx)

{

	struct pp_smu_funcs_rv *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);

	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);



	if (!pp_smu)

		return pp_smu;



	dm_pp_get_funcs_rv(ctx, pp_smu);

	dm_pp_get_funcs(ctx, pp_smu);

	return pp_smu;

}