Commit 0f3bbe0e authored Jan 16, 2023 by Mark Brown Committed by Catalin Marinas Jan 20, 2023

arm64/sysreg: Update system registers for SME 2 and 2.1

FEAT_SME2 and FEAT_SME2P1 introduce several new SME features which can
be enumerated via ID_AA64SMFR0_EL1 and a new register ZT0 access to
which is controlled via SMCR_ELn, add the relevant register description.

Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20221208-arm64-sme2-v4-3-f2fa0aef982f@kernel.org

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

parent 6dabf1fa

arch/arm64/tools/sysreg

+23 −4

Original line number	Original line	Diff line number	Diff line
	@@ -894,6 +894,7 @@ EndEnum
	Enum 27:24 SME		Enum 27:24 SME
	0b0000 NI		0b0000 NI
	0b0001 IMP		0b0001 IMP
			0b0010 SME2
	EndEnum		EndEnum
	Res0 23:20		Res0 23:20
	Enum 19:16 MPAM_frac		Enum 19:16 MPAM_frac
	@@ -975,7 +976,9 @@ Enum 63 FA64
	EndEnum		EndEnum
	Res0 62:60		Res0 62:60
	Enum 59:56 SMEver		Enum 59:56 SMEver
	0b0000 IMP		0b0000 SME
			0b0001 SME2
			0b0010 SME2p1
	EndEnum		EndEnum
	Enum 55:52 I16I64		Enum 55:52 I16I64
	0b0000 NI		0b0000 NI
	@@ -986,7 +989,19 @@ Enum 48 F64F64
	0b0 NI		0b0 NI
	0b1 IMP		0b1 IMP
	EndEnum		EndEnum
	Res0 47:40		Enum 47:44 I16I32
			0b0000 NI
			0b0101 IMP
			EndEnum
			Enum 43 B16B16
			0b0 NI
			0b1 IMP
			EndEnum
			Enum 42 F16F16
			0b0 NI
			0b1 IMP
			EndEnum
			Res0 41:40
	Enum 39:36 I8I32		Enum 39:36 I8I32
	0b0000 NI		0b0000 NI
	0b1111 IMP		0b1111 IMP
	@@ -999,7 +1014,10 @@ Enum 34 B16F32
	0b0 NI		0b0 NI
	0b1 IMP		0b1 IMP
	EndEnum		EndEnum
	Res0 33		Enum 33 BI32I32
			0b0 NI
			0b1 IMP
			EndEnum
	Enum 32 F32F32		Enum 32 F32F32
	0b0 NI		0b0 NI
	0b1 IMP		0b1 IMP
	@@ -1599,7 +1617,8 @@ EndSysreg
	SysregFields SMCR_ELx		SysregFields SMCR_ELx
	Res0 63:32		Res0 63:32
	Field 31 FA64		Field 31 FA64
	Res0 30:9		Field 30 EZT0
			Res0 29:9
	Raz 8:4		Raz 8:4
	Field 3:0 LEN		Field 3:0 LEN
	EndSysregFields		EndSysregFields