Loading drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +13 −18 Original line number Original line Diff line number Diff line Loading @@ -2925,9 +2925,9 @@ nvkm_device_del(struct nvkm_device **pdevice) } } static inline bool static inline bool nvkm_device_endianness(void __iomem *pri) nvkm_device_endianness(struct nvkm_device *device) { { u32 boot1 = ioread32_native(pri + 0x000004) & 0x01000001; u32 boot1 = nvkm_rd32(device, 0x000004) & 0x01000001; #ifdef __BIG_ENDIAN #ifdef __BIG_ENDIAN if (!boot1) if (!boot1) return false; return false; Loading @@ -2949,7 +2949,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func, struct nvkm_subdev *subdev; struct nvkm_subdev *subdev; u64 mmio_base, mmio_size; u64 mmio_base, mmio_size; u32 boot0, boot1, strap; u32 boot0, boot1, strap; void __iomem *map = NULL; int ret = -EEXIST, i; int ret = -EEXIST, i; unsigned chipset; unsigned chipset; Loading @@ -2976,8 +2975,8 @@ nvkm_device_ctor(const struct nvkm_device_func *func, mmio_size = device->func->resource_size(device, 0); mmio_size = device->func->resource_size(device, 0); if (detect || mmio) { if (detect || mmio) { map = ioremap(mmio_base, mmio_size); device->pri = ioremap(mmio_base, mmio_size); if (map == NULL) { if (device->pri == NULL) { nvdev_error(device, "unable to map PRI\n"); nvdev_error(device, "unable to map PRI\n"); ret = -ENOMEM; ret = -ENOMEM; goto done; goto done; Loading @@ -2987,10 +2986,10 @@ nvkm_device_ctor(const struct nvkm_device_func *func, /* identify the chipset, and determine classes of subdev/engines */ /* identify the chipset, and determine classes of subdev/engines */ if (detect) { if (detect) { /* switch mmio to cpu's native endianness */ /* switch mmio to cpu's native endianness */ if (!nvkm_device_endianness(map)) { if (!nvkm_device_endianness(device)) { iowrite32_native(0x01000001, map + 0x000004); nvkm_wr32(device, 0x000004, 0x01000001); ioread32_native(map); nvkm_rd32(device, 0x000000); if (!nvkm_device_endianness(map)) { if (!nvkm_device_endianness(device)) { nvdev_error(device, nvdev_error(device, "GPU not supported on big-endian\n"); "GPU not supported on big-endian\n"); ret = -ENOSYS; ret = -ENOSYS; Loading @@ -2998,7 +2997,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, } } } } boot0 = ioread32_native(map + 0x000000); boot0 = nvkm_rd32(device, 0x000000); /* chipset can be overridden for devel/testing purposes */ /* chipset can be overridden for devel/testing purposes */ chipset = nvkm_longopt(device->cfgopt, "NvChipset", 0); chipset = nvkm_longopt(device->cfgopt, "NvChipset", 0); Loading Loading @@ -3157,7 +3156,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, device->chip->name, boot0); device->chip->name, boot0); /* vGPU detection */ /* vGPU detection */ boot1 = ioread32_native(map + 0x000004); boot1 = nvkm_rd32(device, 0x0000004); if (device->card_type >= TU100 && (boot1 & 0x00030000)) { if (device->card_type >= TU100 && (boot1 & 0x00030000)) { nvdev_info(device, "vGPUs are not supported\n"); nvdev_info(device, "vGPUs are not supported\n"); ret = -ENODEV; ret = -ENODEV; Loading @@ -3165,7 +3164,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, } } /* read strapping information */ /* read strapping information */ strap = ioread32_native(map + 0x101000); strap = nvkm_rd32(device, 0x101000); /* determine frequency of timing crystal */ /* determine frequency of timing crystal */ if ( device->card_type <= NV_10 || device->chipset < 0x17 || if ( device->card_type <= NV_10 || device->chipset < 0x17 || Loading @@ -3187,10 +3186,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func, if (!device->name) if (!device->name) device->name = device->chip->name; device->name = device->chip->name; if (mmio) { device->pri = map; } mutex_init(&device->mutex); mutex_init(&device->mutex); for (i = 0; i < NVKM_SUBDEV_NR; i++) { for (i = 0; i < NVKM_SUBDEV_NR; i++) { Loading Loading @@ -3278,9 +3273,9 @@ nvkm_device_ctor(const struct nvkm_device_func *func, ret = 0; ret = 0; done: done: if (map && (!mmio || ret)) { if (device->pri && (!mmio || ret)) { iounmap(device->pri); device->pri = NULL; device->pri = NULL; iounmap(map); } } mutex_unlock(&nv_devices_mutex); mutex_unlock(&nv_devices_mutex); return ret; return ret; Loading Loading
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +13 −18 Original line number Original line Diff line number Diff line Loading @@ -2925,9 +2925,9 @@ nvkm_device_del(struct nvkm_device **pdevice) } } static inline bool static inline bool nvkm_device_endianness(void __iomem *pri) nvkm_device_endianness(struct nvkm_device *device) { { u32 boot1 = ioread32_native(pri + 0x000004) & 0x01000001; u32 boot1 = nvkm_rd32(device, 0x000004) & 0x01000001; #ifdef __BIG_ENDIAN #ifdef __BIG_ENDIAN if (!boot1) if (!boot1) return false; return false; Loading @@ -2949,7 +2949,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func, struct nvkm_subdev *subdev; struct nvkm_subdev *subdev; u64 mmio_base, mmio_size; u64 mmio_base, mmio_size; u32 boot0, boot1, strap; u32 boot0, boot1, strap; void __iomem *map = NULL; int ret = -EEXIST, i; int ret = -EEXIST, i; unsigned chipset; unsigned chipset; Loading @@ -2976,8 +2975,8 @@ nvkm_device_ctor(const struct nvkm_device_func *func, mmio_size = device->func->resource_size(device, 0); mmio_size = device->func->resource_size(device, 0); if (detect || mmio) { if (detect || mmio) { map = ioremap(mmio_base, mmio_size); device->pri = ioremap(mmio_base, mmio_size); if (map == NULL) { if (device->pri == NULL) { nvdev_error(device, "unable to map PRI\n"); nvdev_error(device, "unable to map PRI\n"); ret = -ENOMEM; ret = -ENOMEM; goto done; goto done; Loading @@ -2987,10 +2986,10 @@ nvkm_device_ctor(const struct nvkm_device_func *func, /* identify the chipset, and determine classes of subdev/engines */ /* identify the chipset, and determine classes of subdev/engines */ if (detect) { if (detect) { /* switch mmio to cpu's native endianness */ /* switch mmio to cpu's native endianness */ if (!nvkm_device_endianness(map)) { if (!nvkm_device_endianness(device)) { iowrite32_native(0x01000001, map + 0x000004); nvkm_wr32(device, 0x000004, 0x01000001); ioread32_native(map); nvkm_rd32(device, 0x000000); if (!nvkm_device_endianness(map)) { if (!nvkm_device_endianness(device)) { nvdev_error(device, nvdev_error(device, "GPU not supported on big-endian\n"); "GPU not supported on big-endian\n"); ret = -ENOSYS; ret = -ENOSYS; Loading @@ -2998,7 +2997,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, } } } } boot0 = ioread32_native(map + 0x000000); boot0 = nvkm_rd32(device, 0x000000); /* chipset can be overridden for devel/testing purposes */ /* chipset can be overridden for devel/testing purposes */ chipset = nvkm_longopt(device->cfgopt, "NvChipset", 0); chipset = nvkm_longopt(device->cfgopt, "NvChipset", 0); Loading Loading @@ -3157,7 +3156,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, device->chip->name, boot0); device->chip->name, boot0); /* vGPU detection */ /* vGPU detection */ boot1 = ioread32_native(map + 0x000004); boot1 = nvkm_rd32(device, 0x0000004); if (device->card_type >= TU100 && (boot1 & 0x00030000)) { if (device->card_type >= TU100 && (boot1 & 0x00030000)) { nvdev_info(device, "vGPUs are not supported\n"); nvdev_info(device, "vGPUs are not supported\n"); ret = -ENODEV; ret = -ENODEV; Loading @@ -3165,7 +3164,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, } } /* read strapping information */ /* read strapping information */ strap = ioread32_native(map + 0x101000); strap = nvkm_rd32(device, 0x101000); /* determine frequency of timing crystal */ /* determine frequency of timing crystal */ if ( device->card_type <= NV_10 || device->chipset < 0x17 || if ( device->card_type <= NV_10 || device->chipset < 0x17 || Loading @@ -3187,10 +3186,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func, if (!device->name) if (!device->name) device->name = device->chip->name; device->name = device->chip->name; if (mmio) { device->pri = map; } mutex_init(&device->mutex); mutex_init(&device->mutex); for (i = 0; i < NVKM_SUBDEV_NR; i++) { for (i = 0; i < NVKM_SUBDEV_NR; i++) { Loading Loading @@ -3278,9 +3273,9 @@ nvkm_device_ctor(const struct nvkm_device_func *func, ret = 0; ret = 0; done: done: if (map && (!mmio || ret)) { if (device->pri && (!mmio || ret)) { iounmap(device->pri); device->pri = NULL; device->pri = NULL; iounmap(map); } } mutex_unlock(&nv_devices_mutex); mutex_unlock(&nv_devices_mutex); return ret; return ret; Loading