Loading arch/sh/mm/cache-sh2.c +10 −3 Original line number Diff line number Diff line Loading @@ -16,7 +16,7 @@ #include <asm/cacheflush.h> #include <asm/io.h> void __flush_wback_region(void *start, int size) static void sh2__flush_wback_region(void *start, int size) { unsigned long v; unsigned long begin, end; Loading @@ -37,7 +37,7 @@ void __flush_wback_region(void *start, int size) } } void __flush_purge_region(void *start, int size) static void sh2__flush_purge_region(void *start, int size) { unsigned long v; unsigned long begin, end; Loading @@ -51,7 +51,7 @@ void __flush_purge_region(void *start, int size) CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008); } void __flush_invalidate_region(void *start, int size) static void sh2__flush_invalidate_region(void *start, int size) { #ifdef CONFIG_CACHE_WRITEBACK /* Loading Loading @@ -82,3 +82,10 @@ void __flush_invalidate_region(void *start, int size) CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008); #endif } void __init sh2_cache_init(void) { __flush_wback_region = sh2__flush_wback_region; __flush_purge_region = sh2__flush_purge_region; __flush_invalidate_region = sh2__flush_invalidate_region; } arch/sh/mm/cache.c +6 −0 Original line number Diff line number Diff line Loading @@ -244,6 +244,12 @@ void __init cpu_cache_init(void) __flush_purge_region = noop__flush_region; __flush_invalidate_region = noop__flush_region; if (boot_cpu_data.family == CPU_FAMILY_SH2) { extern void __weak sh2_cache_init(void); sh2_cache_init(); } if ((boot_cpu_data.family == CPU_FAMILY_SH4) || (boot_cpu_data.family == CPU_FAMILY_SH4A) || (boot_cpu_data.family == CPU_FAMILY_SH4AL_DSP)) { Loading Loading
arch/sh/mm/cache-sh2.c +10 −3 Original line number Diff line number Diff line Loading @@ -16,7 +16,7 @@ #include <asm/cacheflush.h> #include <asm/io.h> void __flush_wback_region(void *start, int size) static void sh2__flush_wback_region(void *start, int size) { unsigned long v; unsigned long begin, end; Loading @@ -37,7 +37,7 @@ void __flush_wback_region(void *start, int size) } } void __flush_purge_region(void *start, int size) static void sh2__flush_purge_region(void *start, int size) { unsigned long v; unsigned long begin, end; Loading @@ -51,7 +51,7 @@ void __flush_purge_region(void *start, int size) CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008); } void __flush_invalidate_region(void *start, int size) static void sh2__flush_invalidate_region(void *start, int size) { #ifdef CONFIG_CACHE_WRITEBACK /* Loading Loading @@ -82,3 +82,10 @@ void __flush_invalidate_region(void *start, int size) CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008); #endif } void __init sh2_cache_init(void) { __flush_wback_region = sh2__flush_wback_region; __flush_purge_region = sh2__flush_purge_region; __flush_invalidate_region = sh2__flush_invalidate_region; }
arch/sh/mm/cache.c +6 −0 Original line number Diff line number Diff line Loading @@ -244,6 +244,12 @@ void __init cpu_cache_init(void) __flush_purge_region = noop__flush_region; __flush_invalidate_region = noop__flush_region; if (boot_cpu_data.family == CPU_FAMILY_SH2) { extern void __weak sh2_cache_init(void); sh2_cache_init(); } if ((boot_cpu_data.family == CPU_FAMILY_SH4) || (boot_cpu_data.family == CPU_FAMILY_SH4A) || (boot_cpu_data.family == CPU_FAMILY_SH4AL_DSP)) { Loading