Commit 10cdc1a7 authored by Mike Frysinger's avatar Mike Frysinger
Browse files

Blackfin: unify pll.h headers 



Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent 73a40064

arch/blackfin/include/mach-common/pll.h

0 → 100644
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/*

 * Copyright 2005-2010 Analog Devices Inc.

 *

 * Licensed under the GPL-2 or later.

 */



#ifndef _MACH_COMMON_PLL_H

#define _MACH_COMMON_PLL_H



#ifndef __ASSEMBLY__



#include <asm/blackfin.h>

#include <asm/irqflags.h>



#ifndef bfin_iwr_restore

static inline void

bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)

{

#ifdef SIC_IWR

	bfin_write_SIC_IWR(iwr0);

#else

	bfin_write_SIC_IWR0(iwr0);

# ifdef SIC_IWR1

	bfin_write_SIC_IWR1(iwr1);

# endif

# ifdef SIC_IWR2

	bfin_write_SIC_IWR2(iwr2);

# endif

#endif

}

#endif



#ifndef bfin_iwr_save

static inline void

bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,

              unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)

{

#ifdef SIC_IWR

	*iwr0 = bfin_read_SIC_IWR();

#else

	*iwr0 = bfin_read_SIC_IWR0();

# ifdef SIC_IWR1

	*iwr1 = bfin_read_SIC_IWR1();

# endif

# ifdef SIC_IWR2

	*iwr2 = bfin_read_SIC_IWR2();

# endif

#endif

	bfin_iwr_restore(niwr0, niwr1, niwr2);

}

#endif



static inline void _bfin_write_pll_relock(u32 addr, unsigned int val)

{

	unsigned long flags, iwr0, iwr1, iwr2;



	if (val == bfin_read_PLL_CTL())

		return;



	flags = hard_local_irq_save();

	/* Enable the PLL Wakeup bit in SIC IWR */

	bfin_iwr_save(IWR_ENABLE(0), 0, 0, &iwr0, &iwr1, &iwr2);



	bfin_write16(addr, val);

	SSYNC();

	asm("IDLE;");



	bfin_iwr_restore(iwr0, iwr1, iwr2);

	hard_local_irq_restore(flags);

}



/* Writing to PLL_CTL initiates a PLL relock sequence */

static inline void bfin_write_PLL_CTL(unsigned int val)

{

	_bfin_write_pll_relock(PLL_CTL, val);

}



/* Writing to VR_CTL initiates a PLL relock sequence */

static inline void bfin_write_VR_CTL(unsigned int val)

{

	_bfin_write_pll_relock(VR_CTL, val);

}



#endif



#endif

arch/blackfin/mach-bf518/include/mach/pll.h

+1 −63
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/*

 * Copyright 2008 Analog Devices Inc.

 *

 * Licensed under the GPL-2 or later

 */



#ifndef _MACH_PLL_H

#define _MACH_PLL_H



#include <asm/blackfin.h>

#include <asm/irqflags.h>



/* Writing to PLL_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_PLL_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_PLL_CTL())

		return;



	flags = hard_local_irq_save();

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(PLL_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	hard_local_irq_restore(flags);

}



/* Writing to VR_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_VR_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_VR_CTL())

		return;



	flags = hard_local_irq_save();

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(VR_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	hard_local_irq_restore(flags);

}



#endif /* _MACH_PLL_H */
 
#include <mach-common/pll.h>

arch/blackfin/mach-bf527/include/mach/pll.h

+1 −63
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/*

 * Copyright 2007-2008 Analog Devices Inc.

 *

 * Licensed under the GPL-2 or later

 */



#ifndef _MACH_PLL_H

#define _MACH_PLL_H



#include <asm/blackfin.h>

#include <asm/irqflags.h>



/* Writing to PLL_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_PLL_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_PLL_CTL())

		return;



	flags = hard_local_irq_save();

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(PLL_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	hard_local_irq_restore(flags);

}



/* Writing to VR_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_VR_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_VR_CTL())

		return;



	flags = hard_local_irq_save();

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(VR_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	hard_local_irq_restore(flags);

}



#endif /* _MACH_PLL_H */
 
#include <mach-common/pll.h>

arch/blackfin/mach-bf533/include/mach/pll.h

+1 −57
Original line number Diff line number Diff line 
/*

 * Copyright 2005-2008 Analog Devices Inc.

 *

 * Licensed under the GPL-2 or later

 */



#ifndef _MACH_PLL_H

#define _MACH_PLL_H



#include <asm/blackfin.h>

#include <asm/irqflags.h>



/* Writing to PLL_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_PLL_CTL(unsigned int val)

{

	unsigned long flags, iwr;



	if (val == bfin_read_PLL_CTL())

		return;



	flags = hard_local_irq_save();

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr = bfin_read32(SIC_IWR);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR, IWR_ENABLE(0));



	bfin_write16(PLL_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR, iwr);

	hard_local_irq_restore(flags);

}



/* Writing to VR_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_VR_CTL(unsigned int val)

{

	unsigned long flags, iwr;



	if (val == bfin_read_VR_CTL())

		return;



	flags = hard_local_irq_save();

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr = bfin_read32(SIC_IWR);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR, IWR_ENABLE(0));



	bfin_write16(VR_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR, iwr);

	hard_local_irq_restore(flags);

}



#endif /* _MACH_PLL_H */
 
#include <mach-common/pll.h>

arch/blackfin/mach-bf537/include/mach/pll.h

+1 −57
Original line number Diff line number Diff line 
/*

 * Copyright 2005-2008 Analog Devices Inc.

 *

 * Licensed under the GPL-2 or later

 */



#ifndef _MACH_PLL_H

#define _MACH_PLL_H



#include <asm/blackfin.h>

#include <asm/irqflags.h>



/* Writing to PLL_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_PLL_CTL(unsigned int val)

{

	unsigned long flags, iwr;



	if (val == bfin_read_PLL_CTL())

		return;



	flags = hard_local_irq_save();

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr = bfin_read32(SIC_IWR);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR, IWR_ENABLE(0));



	bfin_write16(PLL_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR, iwr);

	hard_local_irq_restore(flags);

}



/* Writing to VR_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_VR_CTL(unsigned int val)

{

	unsigned long flags, iwr;



	if (val == bfin_read_VR_CTL())

		return;



	flags = hard_local_irq_save();

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr = bfin_read32(SIC_IWR);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR, IWR_ENABLE(0));



	bfin_write16(VR_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR, iwr);

	hard_local_irq_restore(flags);

}



#endif /* _MACH_PLL_H */
 
#include <mach-common/pll.h>