Commit 1141301c authored by Sai Prakash Ranjan's avatar Sai Prakash Ranjan Committed by Greg Kroah-Hartman
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dt-bindings: coresight: Change CPU phandle to required property 

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parent a94de2e7

Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt

+2 −2
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@@ -26,8 +26,8 @@ Required properties: 
		processor core is clocked by the internal CPU clock, so it

		is enabled with CPU clock by default.



- cpu : the CPU phandle the debug module is affined to. When omitted

	the module is considered to belong to CPU0.

- cpu : the CPU phandle the debug module is affined to. Do not assume it

        to default to CPU0 if omitted.



Optional properties:

Documentation/devicetree/bindings/arm/coresight.txt

+5 −3
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@@ -59,6 +59,11 @@ its hardware characteristcs. 


	* port or ports: see "Graph bindings for Coresight" below.



* Additional required property for Embedded Trace Macrocell (version 3.x and

  version 4.x):

	* cpu: the cpu phandle this ETM/PTM is affined to. Do not

	  assume it to default to CPU0 if omitted.



* Additional required properties for System Trace Macrocells (STM):

	* reg: along with the physical base address and length of the register

	  set as described above, another entry is required to describe the
@@ -87,9 +92,6 @@ its hardware characteristcs. 
	* arm,cp14: must be present if the system accesses ETM/PTM management

	  registers via co-processor 14.



	* cpu: the cpu phandle this ETM/PTM is affined to. When omitted the

	  source is considered to belong to CPU0.



* Optional property for TMC:



	* arm,buffer-size: size of contiguous buffer space for TMC ETR