Commit 116f7cc4 authored by Douglas Anderson's avatar Douglas Anderson Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sc7280: Add herobrine-r1 



Add the new herobrine-r1. Note that this is pretty much a re-design
compared to herobrine-r0 so we don't attempt any dtsi to share stuff
between them.

This patch attempts to define things at 3 levels:

1. The Qcard level. Herobrine includes a Qcard PCB and the Qcard PCB
   is supposed to be the same (modulo stuffing options) across
   multiple boards, so trying to define what's there hopefully makes
   sense. NOTE that newer "CRD" boards from Qualcomm also use
   Qcard. When support for CRD3 is added hopefully it can use the
   Qcard include (and perhaps we should even evaluate it using
   herobrine.dtsi?)
2. The herobrine "baseboard" level. Right now most stuff is here with
   the exception of things that we _know_ will be different per
   board. We know that not all boards will have the same set of eMMC,
   nvme, and SD. We also know that the exact pin names are likely to
   be different.
3. The actual "board" level, AKA herobrine-rev1.

NOTES:
- This boots to command prompt. We're still waiting on the PWM driver.
- This assumes LTE for now. Once it's clear how WiFi-only SKUs will
  work we expect some small changes.

Signed-off-by: default avatarDouglas Anderson <dianders@chromium.org>
Reviewed-by: default avatarMatthias Kaehlcke <mka@chromium.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220204140550.v4.1.I5604b7af908e8bbe709ac037a6a8a6ba8a2bfa94@changeid
parent 067b2b36

arch/arm64/boot/dts/qcom/Makefile

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@@ -84,6 +84,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb 
dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-r1.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-r1.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-r1-lte.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-r1-lte.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-herobrine-r0.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-herobrine-r0.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-herobrine-r1.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-idp.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-idp.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-idp2.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-idp2.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-crd.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-crd.dtb

arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts

+1 −2
Original line number Original line Diff line number Diff line
@@ -25,8 +25,7 @@ 




/ {

/ {

	model = "Google Herobrine (rev0)";

	model = "Google Herobrine (rev0)";

	compatible = "google,herobrine",

	compatible = "google,herobrine-rev0", "qcom,sc7280";

		     "qcom,sc7280";

};

};





/ {

/ {

arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Google Herobrine board device tree source

 *

 * Copyright 2022 Google LLC.

 */



/dts-v1/;



#include "sc7280-herobrine.dtsi"



/ {

	model = "Google Herobrine (rev1+)";

	compatible = "google,herobrine", "qcom,sc7280";

};



/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */



&ap_spi_fp {

	status = "okay";

};



/*

 * Although the trackpad is really part of the herobrine baseboard, we'll

 * put the actual definition in the board device tree since different boards

 * might hook up different trackpads (or no i2c trackpad at all in the case

 * of tablets / detachables).

 */

ap_tp_i2c: &i2c0 {

	status = "okay";

	clock-frequency = <400000>;



	trackpad: trackpad@15 {

		compatible = "elan,ekth3000";

		reg = <0x15>;

		pinctrl-names = "default";

		pinctrl-0 = <&tp_int_odl>;



		interrupt-parent = <&tlmm>;

		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;



		vcc-supply = <&pp3300_z1>;



		wakeup-source;

	};

};



/*

 * The touchscreen connector might come off the Qcard, at least in the case of

 * eDP. Like the trackpad, we'll put it in the board device tree file since

 * different boards have different touchscreens.

 */

ts_i2c: &i2c13 {

	status = "okay";

	clock-frequency = <400000>;



	ap_ts: touchscreen@5c {

		compatible = "hid-over-i2c";

		reg = <0x5c>;

		pinctrl-names = "default";

		pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>;



		interrupt-parent = <&tlmm>;

		interrupts = <55 IRQ_TYPE_LEVEL_LOW>;



		post-power-on-delay-ms = <500>;

		hid-descr-addr = <0x0000>;



		vdd-supply = <&ts_avdd>;

	};

};



/* For nvme */

&pcie1 {

	status = "okay";

};



/* For nvme */

&pcie1_phy {

	status = "okay";

};



/* For eMMC */

&sdhc_1 {

	status = "okay";

};



/* For SD Card */

&sdhc_2 {

	status = "okay";

};



/* PINCTRL - BOARD-SPECIFIC */



/*

 * Methodology for gpio-line-names:

 * - If a pin goes to herobrine board and is named it gets that name.

 * - If a pin goes to herobrine board and is not named, it gets no name.

 * - If a pin is totally internal to Qcard then it gets Qcard name.

 * - If a pin is not hooked up on Qcard, it gets no name.

 */



&pm8350c_gpios {

	gpio-line-names = "FLASH_STROBE_1",		/* 1 */

			  "AP_SUSPEND",

			  "PM8008_1_RST_N",

			  "",

			  "",

			  "",

			  "PMIC_EDP_BL_EN",

			  "PMIC_EDP_BL_PWM",

			  "";

};



&tlmm {

	gpio-line-names = "AP_TP_I2C_SDA",		/* 0 */

			  "AP_TP_I2C_SCL",

			  "SSD_RST_L",

			  "PE_WAKE_ODL",

			  "AP_SAR_SDA",

			  "AP_SAR_SCL",

			  "PRB_SC_GPIO_6",

			  "TP_INT_ODL",

			  "HP_I2C_SDA",

			  "HP_I2C_SCL",



			  "GNSS_L1_EN",			/* 10 */

			  "GNSS_L5_EN",

			  "SPI_AP_MOSI",

			  "SPI_AP_MISO",

			  "SPI_AP_CLK",

			  "SPI_AP_CS0_L",

			  /*

			   * AP_FLASH_WP is crossystem ABI. Schematics

			   * call it BIOS_FLASH_WP_OD.

			   */

			  "AP_FLASH_WP",

			  "",

			  "AP_EC_INT_L",

			  "",



			  "UF_CAM_RST_L",		/* 20 */

			  "WF_CAM_RST_L",

			  "UART_AP_TX_DBG_RX",

			  "UART_DBG_TX_AP_RX",

			  "",

			  "PM8008_IRQ_1",

			  "HOST2WLAN_SOL",

			  "WLAN2HOST_SOL",

			  "MOS_BT_UART_CTS",

			  "MOS_BT_UART_RFR",



			  "MOS_BT_UART_TX",		/* 30 */

			  "MOS_BT_UART_RX",

			  "PRB_SC_GPIO_32",

			  "HUB_RST_L",

			  "",

			  "",

			  "AP_SPI_FP_MISO",

			  "AP_SPI_FP_MOSI",

			  "AP_SPI_FP_CLK",

			  "AP_SPI_FP_CS_L",



			  "AP_EC_SPI_MISO",		/* 40 */

			  "AP_EC_SPI_MOSI",

			  "AP_EC_SPI_CLK",

			  "AP_EC_SPI_CS_L",

			  "LCM_RST_L",

			  "EARLY_EUD_N",

			  "",

			  "DP_HOT_PLUG_DET",

			  "IO_BRD_MLB_ID0",

			  "IO_BRD_MLB_ID1",



			  "IO_BRD_MLB_ID2",		/* 50 */

			  "SSD_EN",

			  "TS_I2C_SDA_CONN",

			  "TS_I2C_CLK_CONN",

			  "TS_RST_CONN",

			  "TS_INT_CONN",

			  "AP_I2C_TPM_SDA",

			  "AP_I2C_TPM_SCL",

			  "PRB_SC_GPIO_58",

			  "PRB_SC_GPIO_59",



			  "EDP_HOT_PLUG_DET_N",		/* 60 */

			  "FP_TO_AP_IRQ_L",

			  "",

			  "AMP_EN",

			  "CAM0_MCLK_GPIO_64",

			  "CAM1_MCLK_GPIO_65",

			  "WF_CAM_MCLK",

			  "PRB_SC_GPIO_67",

			  "FPMCU_BOOT0",

			  "UF_CAM_SDA",



			  "UF_CAM_SCL",			/* 70 */

			  "",

			  "",

			  "WF_CAM_SDA",

			  "WF_CAM_SCL",

			  "",

			  "",

			  "EN_FP_RAILS",

			  "FP_RST_L",

			  "PCIE1_CLKREQ_ODL",



			  "EN_PP3300_DX_EDP",		/* 80 */

			  "SC_GPIO_81",

			  "FORCED_USB_BOOT",

			  "WCD_RESET_N",

			  "MOS_WLAN_EN",

			  "MOS_BT_EN",

			  "MOS_SW_CTRL",

			  "MOS_PCIE0_RST",

			  "MOS_PCIE0_CLKREQ_N",

			  "MOS_PCIE0_WAKE_N",



			  "MOS_LAA_AS_EN",		/* 90 */

			  "SD_CD_ODL",

			  "",

			  "",

			  "MOS_BT_WLAN_SLIMBUS_CLK",

			  "MOS_BT_WLAN_SLIMBUS_DAT0",

			  "HP_MCLK",

			  "HP_BCLK",

			  "HP_DOUT",

			  "HP_DIN",



			  "HP_LRCLK",			/* 100 */

			  "HP_IRQ",

			  "",

			  "",

			  "GSC_AP_INT_ODL",

			  "EN_PP3300_CODEC",

			  "AMP_BCLK",

			  "AMP_DIN",

			  "AMP_LRCLK",

			  "UIM1_DATA_GPIO_109",



			  "UIM1_CLK_GPIO_110",		/* 110 */

			  "UIM1_RESET_GPIO_111",

			  "PRB_SC_GPIO_112",

			  "UIM0_DATA",

			  "UIM0_CLK",

			  "UIM0_RST",

			  "UIM0_PRESENT_ODL",

			  "SDM_RFFE0_CLK",

			  "SDM_RFFE0_DATA",

			  "WF_CAM_EN",



			  "FASTBOOT_SEL_0",		/* 120 */

			  "SC_GPIO_121",

			  "FASTBOOT_SEL_1",

			  "SC_GPIO_123",

			  "FASTBOOT_SEL_2",

			  "SM_RFFE4_CLK_GRFC_8",

			  "SM_RFFE4_DATA_GRFC_9",

			  "WLAN_COEX_UART1_RX",

			  "WLAN_COEX_UART1_TX",

			  "PRB_SC_GPIO_129",



			  "LCM_ID0",			/* 130 */

			  "LCM_ID1",

			  "",

			  "SDR_QLINK_REQ",

			  "SDR_QLINK_EN",

			  "QLINK0_WMSS_RESET_N",

			  "SMR526_QLINK1_REQ",

			  "SMR526_QLINK1_EN",

			  "SMR526_QLINK1_WMSS_RESET_N",

			  "PRB_SC_GPIO_139",



			  "SAR1_IRQ_ODL",		/* 140 */

			  "SAR0_IRQ_ODL",

			  "PRB_SC_GPIO_142",

			  "",

			  "WCD_SWR_TX_CLK",

			  "WCD_SWR_TX_DATA0",

			  "WCD_SWR_TX_DATA1",

			  "WCD_SWR_RX_CLK",

			  "WCD_SWR_RX_DATA0",

			  "WCD_SWR_RX_DATA1",



			  "DMIC01_CLK",			/* 150 */

			  "DMIC01_DATA",

			  "DMIC23_CLK",

			  "DMIC23_DATA",

			  "",

			  "",

			  "EC_IN_RW_ODL",

			  "HUB_EN",

			  "WCD_SWR_TX_DATA2",

			  "",



			  "",				/* 160 */

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",

			  "",



			  "",				/* 170 */

			  "MOS_BLE_UART_TX",

			  "MOS_BLE_UART_RX",

			  "",

			  "",

			  "";

};

arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Google Herobrine baseboard device tree source

 *

 * The set of things in this file is a bit loosely defined. It's roughly

 * defined as the set of things that the child boards happen to have in

 * common. Since all of the child boards started from the same original

 * design this is hopefully a large set of things but as more derivatives

 * appear things may "bubble down" out of this file. For things that are

 * part of the reference design but might not exist on child nodes we will

 * follow the lead of the SoC dtsi files and leave their status as "disabled".

 *

 * Copyright 2022 Google LLC.

 */



#include <dt-bindings/input/gpio-keys.h>

#include <dt-bindings/input/input.h>



#include "sc7280-qcard.dtsi"

#include "sc7280-chrome-common.dtsi"



/ {

	chosen {

		stdout-path = "serial0:115200n8";

	};



	/*

	 * FIXED REGULATORS

	 *

	 * Sort order:

	 * 1. parents above children.

	 * 2. higher voltage above lower voltage.

	 * 3. alphabetically by node name.

	 */



	/* This is the top level supply and variable voltage */

	ppvar_sys: ppvar-sys-regulator {

		compatible = "regulator-fixed";

		regulator-name = "ppvar_sys";

		regulator-always-on;

		regulator-boot-on;

	};



	/* This divides ppvar_sys by 2, so voltage is variable */

	src_vph_pwr: src-vph-pwr-regulator {

		compatible = "regulator-fixed";

		regulator-name = "src_vph_pwr";



		/* EC turns on with switchcap_on; always on for AP */

		regulator-always-on;

		regulator-boot-on;



		vin-supply = <&ppvar_sys>;

	};



	pp5000_s5: pp5000-s5-regulator {

		compatible = "regulator-fixed";

		regulator-name = "pp5000_s5";



		/* EC turns on with en_pp5000_s5; always on for AP */

		regulator-always-on;

		regulator-boot-on;

		regulator-min-microvolt = <5000000>;

		regulator-max-microvolt = <5000000>;



		vin-supply = <&ppvar_sys>;

	};



	pp3300_z1: pp3300-z1-regulator {

		compatible = "regulator-fixed";

		regulator-name = "pp3300_z1";



		/* EC turns on with en_pp3300_z1; always on for AP */

		regulator-always-on;

		regulator-boot-on;

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;



		vin-supply = <&ppvar_sys>;

	};



	pp3300_codec: pp3300-codec-regulator {

		compatible = "regulator-fixed";

		regulator-name = "pp3300_codec";



		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;



		gpio = <&tlmm 105 GPIO_ACTIVE_HIGH>;

		enable-active-high;

		pinctrl-names = "default";

		pinctrl-0 = <&en_pp3300_codec>;



		vin-supply = <&pp3300_z1>;

	};



	pp3300_left_in_mlb: pp3300-left-in-mlb-regulator {

		compatible = "regulator-fixed";

		regulator-name = "pp3300_left_in_mlb";



		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;



		gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>;

		enable-active-high;

		pinctrl-names = "default";

		pinctrl-0 = <&en_pp3300_dx_edp>;



		vin-supply = <&pp3300_z1>;

	};



	pp3300_mcu_fp:

	pp3300_fp_ls:

	pp3300_fp_mcu: pp3300-fp-regulator {

		compatible = "regulator-fixed";

		regulator-name = "pp3300_fp";



		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;



		regulator-boot-on;

		regulator-always-on;



		/*

		 * WARNING: it is intentional that GPIO 77 isn't listed here.

		 * The userspace script for updating the fingerprint firmware

		 * needs to control the FP regulators during a FW update,

		 * hence the signal can't be owned by the kernel regulator.

		 */



		pinctrl-names = "default";

		pinctrl-0 = <&en_fp_rails>;



		vin-supply = <&pp3300_z1>;

	};



	pp3300_hub: pp3300-hub-regulator {

		compatible = "regulator-fixed";

		regulator-name = "pp3300_hub";



		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;



		regulator-boot-on;

		regulator-always-on;



		gpio = <&tlmm 157 GPIO_ACTIVE_HIGH>;

		enable-active-high;

		pinctrl-names = "default";

		pinctrl-0 = <&hub_en>;



		vin-supply = <&pp3300_z1>;

	};



	pp3300_tp: pp3300-tp-regulator {

		compatible = "regulator-fixed";

		regulator-name = "pp3300_tp";



		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;



		/* AP turns on with PP1800_L18B_S0; always on for AP */

		regulator-always-on;

		regulator-boot-on;



		vin-supply = <&pp3300_z1>;

	};



	pp3300_ssd: pp3300-ssd-regulator {

		compatible = "regulator-fixed";

		regulator-name = "pp3300_ssd";



		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;



		gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>;

		enable-active-high;

		pinctrl-names = "default";

		pinctrl-0 = <&ssd_en>;



		vin-supply = <&pp3300_z1>;

	};



	pp2850_vcm_wf_cam: pp2850-vcm-wf-cam-regulator {

		compatible = "regulator-fixed";

		regulator-name = "pp2850_vcm_wf_cam";



		regulator-min-microvolt = <2850000>;

		regulator-max-microvolt = <2850000>;



		gpio = <&tlmm 119 GPIO_ACTIVE_HIGH>;

		enable-active-high;

		pinctrl-names = "default";

		pinctrl-0 = <&wf_cam_en>;



		vin-supply = <&pp3300_z1>;

	};



	pp2850_wf_cam: pp2850-wf-cam-regulator {

		compatible = "regulator-fixed";

		regulator-name = "pp2850_wf_cam";



		regulator-min-microvolt = <2850000>;

		regulator-max-microvolt = <2850000>;



		gpio = <&tlmm 119 GPIO_ACTIVE_HIGH>;

		enable-active-high;

		/*

		 * The pinconf can only be referenced once so we put it on the

		 * first regulator and comment it out here.

		 *

		 * pinctrl-names = "default";

		 * pinctrl-0 = <&wf_cam_en>;

		 */



		vin-supply = <&pp3300_z1>;

	};



	pp1800_fp: pp1800-fp-regulator {

		compatible = "regulator-fixed";

		regulator-name = "pp1800_fp";



		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <1800000>;



		regulator-boot-on;

		regulator-always-on;



		/*

		 * WARNING: it is intentional that GPIO 77 isn't listed here.

		 * The userspace script for updating the fingerprint firmware

		 * needs to control the FP regulators during a FW update,

		 * hence the signal can't be owned by the kernel regulator.

		 */



		pinctrl-names = "default";

		pinctrl-0 = <&en_fp_rails>;



		vin-supply = <&pp1800_l18b_s0>;

		status = "disabled";

	};



	pp1800_wf_cam: pp1800-wf-cam-regulator {

		compatible = "regulator-fixed";

		regulator-name = "pp1800_wf_cam";



		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <1800000>;



		gpio = <&tlmm 119 GPIO_ACTIVE_HIGH>;

		enable-active-high;

		/*

		 * The pinconf can only be referenced once so we put it on the

		 * first regulator and comment it out here.

		 *

		 * pinctrl-names = "default";

		 * pinctrl-0 = <&wf_cam_en>;

		 */



		vin-supply = <&vreg_l19b_s0>;

	};



	pp1200_wf_cam: pp1200-wf-cam-regulator {

		compatible = "regulator-fixed";

		regulator-name = "pp1200_wf_cam";



		regulator-min-microvolt = <1200000>;

		regulator-max-microvolt = <1200000>;



		gpio = <&tlmm 119 GPIO_ACTIVE_HIGH>;

		enable-active-high;

		/*

		 * The pinconf can only be referenced once so we put it on the

		 * first regulator and comment it out here.

		 *

		 * pinctrl-names = "default";

		 * pinctrl-0 = <&wf_cam_en>;

		 */



		vin-supply = <&pp3300_z1>;

	};



	/* BOARD-SPECIFIC TOP LEVEL NODES */



	pwmleds {

		compatible = "pwm-leds";

		status = "disabled";

		keyboard_backlight: keyboard-backlight {

			status = "disabled";

			label = "cros_ec::kbd_backlight";

			pwms = <&cros_ec_pwm 0>;

			max-brightness = <1023>;

		};

	};

};



/*

 * BOARD-LOCAL NAMES FOR REGULATORS THAT CONNECT TO QCARD

 *

 * Names are only listed here if regulators go somewhere other than a

 * testpoint.

 */



/* From Qcard to our board; ordered by PMIC-ID / rail number */



pp1256_s8b: &vreg_s8b_1p256 {};



pp1800_l18b_s0: &vreg_l18b_1p8 {};

pp1800_l18b:    &vreg_l18b_1p8 {};



vreg_l19b_s0: &vreg_l19b_1p8 {};



pp1800_alc5682: &vreg_l2c_1p8 {};

pp1800_l2c:     &vreg_l2c_1p8 {};



vreg_l4c: &vreg_l4c_1p8_3p0 {};



ppvar_l6c: &vreg_l6c_2p96 {};



pp3000_l7c: &vreg_l7c_3p0 {};



pp1800_prox: &vreg_l8c_1p8 {};

pp1800_l8c:  &vreg_l8c_1p8 {};



pp2950_l9c: &vreg_l9c_2p96 {};



pp1800_lcm:  &vreg_l12c_1p8 {};

pp1800_mipi: &vreg_l12c_1p8 {};

pp1800_l12c: &vreg_l12c_1p8 {};



pp3300_lcm:  &vreg_l13c_3p0 {};

pp3300_mipi: &vreg_l13c_3p0 {};

pp3300_l13c: &vreg_l13c_3p0 {};



/* From our board to Qcard; ordered same as node definition above */



vreg_edp_bl: &ppvar_sys {};



ts_avdd:      &pp3300_left_in_mlb {};

vreg_edp_3p3: &pp3300_left_in_mlb {};



/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */



ap_i2c_tpm: &i2c14 {

	status = "okay";

	clock-frequency = <400000>;



	tpm@50 {

		compatible = "google,cr50";

		reg = <0x50>;



		pinctrl-names = "default";

		pinctrl-0 = <&gsc_ap_int_odl>;



		interrupt-parent = <&tlmm>;

		interrupts = <104 IRQ_TYPE_EDGE_RISING>;

	};

};



/* NVMe drive, enabled on a per-board basis */

&pcie1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pcie1_clkreq_n>, <&ssd_rst_l>, <&pe_wake_odl>;



	perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>;

	vddpe-3v3-supply = <&pp3300_ssd>;

};



&pmk8350_rtc {

	status = "disabled";

};



&qupv3_id_0 {

	status = "okay";

};



&qupv3_id_1 {

	status = "okay";

};



/* SD Card, enabled on a per-board basis */

&sdhc_2 {

	pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd_odl>;

	pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd_odl>;



	vmmc-supply = <&pp2950_l9c>;

	vqmmc-supply = <&ppvar_l6c>;



	cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;

};



/* Fingerprint, enabled on a per-board basis */

ap_spi_fp: &spi9 {

	pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs_gpio_init_high>, <&qup_spi9_cs_gpio>;



	cs-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;



	cros_ec_fp: ec@0 {

		compatible = "google,cros-ec-spi";

		reg = <0>;

		interrupt-parent = <&tlmm>;

		interrupts = <61 IRQ_TYPE_LEVEL_LOW>;

		pinctrl-names = "default";

		pinctrl-0 = <&fp_to_ap_irq_l>, <&fp_rst_l>, <&fpmcu_boot0>;

		spi-max-frequency = <3000000>;

	};

};



ap_ec_spi: &spi10 {

	status = "okay";

	pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>;



	cs-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;



	cros_ec: ec@0 {

		compatible = "google,cros-ec-spi";

		reg = <0>;

		interrupt-parent = <&tlmm>;

		interrupts = <18 IRQ_TYPE_LEVEL_LOW>;

		pinctrl-names = "default";

		pinctrl-0 = <&ap_ec_int_l>;

		spi-max-frequency = <3000000>;



		cros_ec_pwm: ec-pwm {

			compatible = "google,cros-ec-pwm";

			#pwm-cells = <1>;

		};



		i2c_tunnel: i2c-tunnel {

			compatible = "google,cros-ec-i2c-tunnel";

			google,remote-bus = <0>;

			#address-cells = <1>;

			#size-cells = <0>;

		};



		typec {

			compatible = "google,cros-ec-typec";

			#address-cells = <1>;

			#size-cells = <0>;



			usb_c0: connector@0 {

				compatible = "usb-c-connector";

				reg = <0>;

				label = "left";

				power-role = "dual";

				data-role = "host";

				try-power-role = "source";

			};



			usb_c1: connector@1 {

				compatible = "usb-c-connector";

				reg = <1>;

				label = "right";

				power-role = "dual";

				data-role = "host";

				try-power-role = "source";

			};

		};

	};

};



#include <arm/cros-ec-keyboard.dtsi>

#include <arm/cros-ec-sbs.dtsi>



&keyboard_controller {

	function-row-physmap = <

		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */

		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */

		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */

		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */

		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */

		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */

		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */

		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */

		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */

		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */

	>;

	linux,keymap = <

		MATRIX_KEY(0x00, 0x02, KEY_BACK)

		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)

		MATRIX_KEY(0x02, 0x02, KEY_ZOOM)

		MATRIX_KEY(0x01, 0x02, KEY_SCALE)

		MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)

		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)

		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)

		MATRIX_KEY(0x02, 0x09, KEY_MUTE)

		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)

		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)



		CROS_STD_MAIN_KEYMAP

	>;

};



&usb_1 {

	status = "okay";

};



&usb_1_dwc3 {

	dr_mode = "host";

};



&usb_1_hsphy {

	status = "okay";

};



&usb_1_qmpphy {

	status = "okay";

};



&usb_2 {

	status = "okay";

};



&usb_2_dwc3 {

	dr_mode = "host";

};



&usb_2_hsphy {

	status = "okay";

};



/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */



&dp_hot_plug_det {

	bias-disable;

};



&pcie1_clkreq_n {

	bias-pull-up;

	drive-strength = <2>;

};



&qspi_cs0 {

	bias-disable;

	drive-strength = <8>;

};



&qspi_clk {

	bias-disable;

	drive-strength = <8>;

};



&qspi_data01 {

	/* High-Z when no transfers; nice to park the lines */

	bias-pull-up;

	drive-strength = <8>;

};



/* For ap_tp_i2c */

&qup_i2c0_data_clk {

	/* Has external pull */

	bias-disable;

	drive-strength = <2>;

};



/* For ap_i2c_tpm */

&qup_i2c14_data_clk {

	/* Has external pull */

	bias-disable;

	drive-strength = <2>;

};



/* For ap_spi_fp */

&qup_spi9_data_clk {

	bias-disable;

	drive-strength = <2>;

};



/* For ap_spi_fp */

&qup_spi9_cs_gpio {

	bias-disable;

	drive-strength = <2>;

};



/* For ap_ec_spi */

&qup_spi10_data_clk {

	bias-disable;

	drive-strength = <2>;

};



/* For ap_ec_spi */

&qup_spi10_cs_gpio {

	bias-disable;

	drive-strength = <2>;

};



/* For uart_dbg */

&qup_uart5_rx {

	bias-pull-up;

};



/* For uart_dbg */

&qup_uart5_tx {

	bias-disable;

	drive-strength = <2>;

};



&sdc2_clk {

	bias-disable;

	drive-strength = <16>;

};



&sdc2_cmd {

	bias-pull-up;

	drive-strength = <10>;

};



&sdc2_data {

	bias-pull-up;

	drive-strength = <10>;

};



/* PINCTRL - board-specific pinctrl */



&pm7325_gpios {

	/*

	 * On a quick glance it might look like KYPD_VOL_UP_N is used, but

	 * that only passes through to a debug connector and not to the actual

	 * volume up key.

	 */

	status = "disabled"; /* No GPIOs are connected */

};



&pmk8350_gpios {

	status = "disabled"; /* No GPIOs are connected */

};



&tlmm {

	/* pinctrl settings for pins that have no real owners. */

	pinctrl-names = "default";

	pinctrl-0 = <&bios_flash_wp_od>;



	amp_en: amp-en {

		pins = "gpio63";

		function = "gpio";

		bias-disable;

		drive-strength = <2>;

	};



	ap_ec_int_l: ap-ec-int-l {

		pins = "gpio18";

		function = "gpio";

		bias-pull-up;

	};



	bios_flash_wp_od: bios-flash-wp-od {

		pins = "gpio16";

		function = "gpio";

		/* Has external pull */

		bias-disable;

	};



	en_fp_rails: en-fp-rails {

		pins = "gpio77";

		function = "gpio";

		bias-disable;

		drive-strength = <2>;

		output-high;

	};



	en_pp3300_codec: en-pp3300-codec {

		pins = "gpio105";

		function = "gpio";

		bias-disable;

		drive-strength = <2>;

	};



	en_pp3300_dx_edp: en-pp3300-dx-edp {

		pins = "gpio80";

		function = "gpio";

		bias-disable;

		drive-strength = <2>;

	};



	fp_rst_l: fp-rst-l {

		pins = "gpio78";

		function = "gpio";

		bias-disable;

		drive-strength = <2>;

		output-high;

	};



	fp_to_ap_irq_l: fp-to-ap-irq-l {

		pins = "gpio61";

		function = "gpio";

		/* Has external pullup */

		bias-disable;

	};



	fpmcu_boot0: fpmcu-boot0 {

		pins = "gpio68";

		function = "gpio";

		bias-disable;

		output-low;

	};



	gsc_ap_int_odl: gsc-ap-int-odl {

		pins = "gpio104";

		function = "gpio";

		bias-pull-up;

	};



	hp_irq: hp-irq {

		pins = "gpio101";

		function = "gpio";

		bias-pull-up;

	};



	hub_en: hub-en {

		pins = "gpio157";

		function = "gpio";

		bias-disable;

		drive-strength = <2>;

	};



	pe_wake_odl: pe-wake-odl {

		pins = "gpio3";

		function = "gpio";

		/* Has external pull */

		bias-disable;

		drive-strength = <2>;

	};



	/* For ap_spi_fp */

	qup_spi9_cs_gpio_init_high: qup-spi9-cs-gpio-init-high {

		pins = "gpio39";

		function = "gpio";

		output-high;

	};



	/* For ap_ec_spi */

	qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high {

		pins = "gpio43";

		function = "gpio";

		output-high;

	};



	sar0_irq_odl: sar0-irq-odl {

		pins = "gpio141";

		function = "gpio";

		bias-pull-up;

	};



	sar1_irq_odl: sar0-irq-odl {

		pins = "gpio140";

		function = "gpio";

		bias-pull-up;

	};



	sd_cd_odl: sd-cd-odl {

		pins = "gpio91";

		function = "gpio";

		bias-pull-up;

	};



	ssd_en: ssd-en {

		pins = "gpio51";

		function = "gpio";

		bias-disable;

		drive-strength = <2>;

	};



	ssd_rst_l: ssd-rst-l {

		pins = "gpio2";

		function = "gpio";

		bias-disable;

		drive-strength = <2>;

		output-low;

	};



	tp_int_odl: tp-int-odl {

		pins = "gpio7";

		function = "gpio";

		/* Has external pullup */

		bias-disable;

	};



	wf_cam_en: wf-cam-en {

		pins = "gpio119";

		function = "gpio";

		/* Has external pulldown */

		bias-disable;

		drive-strength = <2>;

	};

};

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