Commit 13a390a6 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: add psp funcs for ring write pointer read/write 



The ring write pointer regsiter update is the only part that
is IP specific ones in psp_cmd_submit function.

Add two callbacks for wptr read/write so that we unify the
psp_cmd_submit function for all the ASICs.

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarJohn Clements <john.clements@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 32cc3bf0

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

+5 −0
Original line number Diff line number Diff line
@@ -116,6 +116,8 @@ struct psp_funcs 
	int (*mem_training_init)(struct psp_context *psp);

	void (*mem_training_fini)(struct psp_context *psp);

	int (*mem_training)(struct psp_context *psp, uint32_t ops);

	uint32_t (*ring_get_wptr)(struct psp_context *psp);

	void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);

};



#define AMDGPU_XGMI_MAX_CONNECTED_NODES		64
@@ -346,6 +348,9 @@ struct amdgpu_psp_funcs { 
	((psp)->funcs->ras_cure_posion ? \

	(psp)->funcs->ras_cure_posion(psp, (addr)) : -EINVAL)



#define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))

#define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))



extern const struct amd_ip_funcs psp_ip_funcs;



extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;

drivers/gpu/drm/amd/amdgpu/psp_v10_0.c

+16 −0
Original line number Diff line number Diff line
@@ -407,6 +407,20 @@ static int psp_v10_0_mode1_reset(struct psp_context *psp) 
	return -EINVAL;

}



static uint32_t psp_v10_0_ring_get_wptr(struct psp_context *psp)

{

	struct amdgpu_device *adev = psp->adev;



	return RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);

}



static void psp_v10_0_ring_set_wptr(struct psp_context *psp, uint32_t value)

{

	struct amdgpu_device *adev = psp->adev;



	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);

}



static const struct psp_funcs psp_v10_0_funcs = {

	.init_microcode = psp_v10_0_init_microcode,

	.ring_init = psp_v10_0_ring_init,
@@ -416,6 +430,8 @@ static const struct psp_funcs psp_v10_0_funcs = { 
	.cmd_submit = psp_v10_0_cmd_submit,

	.compare_sram_data = psp_v10_0_compare_sram_data,

	.mode1_reset = psp_v10_0_mode1_reset,

	.ring_get_wptr = psp_v10_0_ring_get_wptr,

	.ring_set_wptr = psp_v10_0_ring_set_wptr,

};



void psp_v10_0_set_psp_funcs(struct psp_context *psp)

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

+26 −0
Original line number Diff line number Diff line
@@ -1068,6 +1068,30 @@ static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops) 
	return 0;

}



static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)

{

	uint32_t data;

	struct amdgpu_device *adev = psp->adev;



	if (psp_v11_0_support_vmr_ring(psp))

		data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);

	else

		data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);



	return data;

}



static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value)

{

	struct amdgpu_device *adev = psp->adev;



	if (psp_v11_0_support_vmr_ring(psp)) {

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);

	} else

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);

}



static const struct psp_funcs psp_v11_0_funcs = {

	.init_microcode = psp_v11_0_init_microcode,

	.bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
@@ -1091,6 +1115,8 @@ static const struct psp_funcs psp_v11_0_funcs = { 
	.mem_training_init = psp_v11_0_memory_training_init,

	.mem_training_fini = psp_v11_0_memory_training_fini,

	.mem_training = psp_v11_0_memory_training,

	.ring_get_wptr = psp_v11_0_ring_get_wptr,

	.ring_set_wptr = psp_v11_0_ring_set_wptr,

};



void psp_v11_0_set_psp_funcs(struct psp_context *psp)

drivers/gpu/drm/amd/amdgpu/psp_v12_0.c

+26 −0
Original line number Diff line number Diff line
@@ -547,6 +547,30 @@ static int psp_v12_0_mode1_reset(struct psp_context *psp) 
	return 0;

}



static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp)

{

	uint32_t data;

	struct amdgpu_device *adev = psp->adev;



	if (psp_v12_0_support_vmr_ring(psp))

		data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);

	else

		data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);



	return data;

}



static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value)

{

	struct amdgpu_device *adev = psp->adev;



	if (psp_v12_0_support_vmr_ring(psp)) {

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);

	} else

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);

}



static const struct psp_funcs psp_v12_0_funcs = {

	.init_microcode = psp_v12_0_init_microcode,

	.bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
@@ -558,6 +582,8 @@ static const struct psp_funcs psp_v12_0_funcs = { 
	.cmd_submit = psp_v12_0_cmd_submit,

	.compare_sram_data = psp_v12_0_compare_sram_data,

	.mode1_reset = psp_v12_0_mode1_reset,

	.ring_get_wptr = psp_v12_0_ring_get_wptr,

	.ring_set_wptr = psp_v12_0_ring_set_wptr,

};



void psp_v12_0_set_psp_funcs(struct psp_context *psp)

drivers/gpu/drm/amd/amdgpu/psp_v3_1.c

+27 −0
Original line number Diff line number Diff line
@@ -642,6 +642,31 @@ static bool psp_v3_1_support_vmr_ring(struct psp_context *psp) 
	return false;

}



static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp)

{

	uint32_t data;

	struct amdgpu_device *adev = psp->adev;



	if (psp_v3_1_support_vmr_ring(psp))

		data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);

	else

		data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);

	return data;

}



static void psp_v3_1_ring_set_wptr(struct psp_context *psp, uint32_t value)

{

	struct amdgpu_device *adev = psp->adev;



	if (psp_v3_1_support_vmr_ring(psp)) {

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);

		/* send interrupt to PSP for SRIOV ring write pointer update */

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,

			GFX_CTRL_CMD_ID_CONSUME_CMD);

	} else

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);

}



static const struct psp_funcs psp_v3_1_funcs = {

	.init_microcode = psp_v3_1_init_microcode,

	.bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
@@ -655,6 +680,8 @@ static const struct psp_funcs psp_v3_1_funcs = { 
	.smu_reload_quirk = psp_v3_1_smu_reload_quirk,

	.mode1_reset = psp_v3_1_mode1_reset,

	.support_vmr_ring = psp_v3_1_support_vmr_ring,

	.ring_get_wptr = psp_v3_1_ring_get_wptr,

	.ring_set_wptr = psp_v3_1_ring_set_wptr,

};



void psp_v3_1_set_psp_funcs(struct psp_context *psp)