Commit 13d1b957 authored by Ard Biesheuvel's avatar Ard Biesheuvel Committed by Russell King
Browse files

ARM: 8221/1: PJ4: allow building in Thumb-2 mode 



Two files that get included when building the multi_v7_defconfig target
fail to build when selecting THUMB2_KERNEL for this configuration.

In both cases, we can just build the file as ARM code, as none of its
symbols are exported to modules, so there are no interworking concerns.
In the iwmmxt.S case, add ENDPROC() declarations so the symbols are
annotated as functions, resulting in the linker to emit the appropriate
mode switches.

Acked-by: default avatarNicolas Pitre <nico@linaro.org>
Tested-by: default avatarOlof Johansson <olof@lixom.net>
Signed-off-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent f3a04202

arch/arm/kernel/Makefile

+1 −0
Original line number Original line Diff line number Diff line
@@ -85,6 +85,7 @@ obj-$(CONFIG_CPU_PJ4B) += pj4-cp0.o 
obj-$(CONFIG_IWMMXT)		+= iwmmxt.o

obj-$(CONFIG_IWMMXT)		+= iwmmxt.o

obj-$(CONFIG_PERF_EVENTS)	+= perf_regs.o

obj-$(CONFIG_PERF_EVENTS)	+= perf_regs.o

obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event.o perf_event_cpu.o

obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event.o perf_event_cpu.o

CFLAGS_pj4-cp0.o		:= -marm

AFLAGS_iwmmxt.o			:= -Wa,-mcpu=iwmmxt

AFLAGS_iwmmxt.o			:= -Wa,-mcpu=iwmmxt

obj-$(CONFIG_ARM_CPU_TOPOLOGY)  += topology.o

obj-$(CONFIG_ARM_CPU_TOPOLOGY)  += topology.o

arch/arm/kernel/iwmmxt.S

+13 −0
Original line number Original line Diff line number Diff line
@@ -58,6 +58,7 @@ 
#define MMX_SIZE		(0x98)

#define MMX_SIZE		(0x98)





	.text

	.text

	.arm





/*

/*

 * Lazy switching of Concan coprocessor context

 * Lazy switching of Concan coprocessor context
@@ -182,6 +183,8 @@ concan_load: 
	tmcr	wCon, r2

	tmcr	wCon, r2

	ret	lr

	ret	lr





ENDPROC(iwmmxt_task_enable)



/*

/*

 * Back up Concan regs to save area and disable access to them

 * Back up Concan regs to save area and disable access to them

 * (mainly for gdb or sleep mode usage)

 * (mainly for gdb or sleep mode usage)
@@ -232,6 +235,8 @@ ENTRY(iwmmxt_task_disable) 
1:	msr	cpsr_c, ip			@ restore interrupt mode

1:	msr	cpsr_c, ip			@ restore interrupt mode

	ldmfd	sp!, {r4, pc}

	ldmfd	sp!, {r4, pc}





ENDPROC(iwmmxt_task_disable)



/*

/*

 * Copy Concan state to given memory address

 * Copy Concan state to given memory address

 *

 *
@@ -268,6 +273,8 @@ ENTRY(iwmmxt_task_copy) 
	msr	cpsr_c, ip			@ restore interrupt mode

	msr	cpsr_c, ip			@ restore interrupt mode

	ret	r3

	ret	r3





ENDPROC(iwmmxt_task_copy)



/*

/*

 * Restore Concan state from given memory address

 * Restore Concan state from given memory address

 *

 *
@@ -304,6 +311,8 @@ ENTRY(iwmmxt_task_restore) 
	msr	cpsr_c, ip			@ restore interrupt mode

	msr	cpsr_c, ip			@ restore interrupt mode

	ret	r3

	ret	r3





ENDPROC(iwmmxt_task_restore)



/*

/*

 * Concan handling on task switch

 * Concan handling on task switch

 *

 *
@@ -335,6 +344,8 @@ ENTRY(iwmmxt_task_switch) 
	mrc	p15, 0, r1, c2, c0, 0

	mrc	p15, 0, r1, c2, c0, 0

	sub	pc, lr, r1, lsr #32		@ cpwait and return

	sub	pc, lr, r1, lsr #32		@ cpwait and return





ENDPROC(iwmmxt_task_switch)



/*

/*

 * Remove Concan ownership of given task

 * Remove Concan ownership of given task

 *

 *
@@ -353,6 +364,8 @@ ENTRY(iwmmxt_task_release) 
	msr	cpsr_c, r2			@ restore interrupts

	msr	cpsr_c, r2			@ restore interrupts

	ret	lr

	ret	lr





ENDPROC(iwmmxt_task_release)



	.data

	.data

concan_owner:

concan_owner:

	.word	0

	.word	0