Commit 13de7f46 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/fifo: convert to new-style nvkm_engine 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 70aa8670

drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h

+17 −66
Original line number Diff line number Diff line 
#ifndef __NVKM_FIFO_H__

#define __NVKM_FIFO_H__

#define nvkm_fifo_chan(p) container_of((p), struct nvkm_fifo_chan, object)

#define nvkm_fifo(p) container_of((p), struct nvkm_fifo, engine)

#include <core/engine.h>

#include <core/event.h>
@@ -33,46 +31,21 @@ struct nvkm_fifo_chan { 


extern const struct nvkm_object_func nvkm_fifo_chan_func;



#include <core/gpuobj.h>

struct nvkm_fifo_base {

	struct nvkm_gpuobj gpuobj;

};



#define nvkm_fifo_context_create(p,e,c,g,s,a,f,d)                           \

	nvkm_gpuobj_create((p), (e), (c), NV_ENGCTX_CLASS, (g), (s), (a), (f), (d))

#define nvkm_fifo_context_destroy(p)                                        \

	nvkm_gpuobj_destroy(&(p)->gpuobj)

#define nvkm_fifo_context_init(p)                                           \

	nvkm_gpuobj_init(&(p)->gpuobj)

#define nvkm_fifo_context_fini(p,s)                                         \

	nvkm_gpuobj_fini(&(p)->gpuobj, (s))



#define _nvkm_fifo_context_dtor _nvkm_gpuobj_dtor

#define _nvkm_fifo_context_init _nvkm_gpuobj_init

#define _nvkm_fifo_context_fini _nvkm_gpuobj_fini

#define _nvkm_fifo_context_rd32 _nvkm_gpuobj_rd32

#define _nvkm_fifo_context_wr32 _nvkm_gpuobj_wr32



struct nvkm_fifo {

	struct nvkm_engine engine;

	const struct nvkm_fifo_func *func;



	struct nvkm_event cevent; /* channel creation event */

	struct nvkm_event uevent; /* async user trigger */

	struct nvkm_engine engine;



	DECLARE_BITMAP(mask, NVKM_FIFO_CHID_NR);

	int nr;

	struct list_head chan;

	spinlock_t lock;



	void (*pause)(struct nvkm_fifo *, unsigned long *);

	void (*start)(struct nvkm_fifo *, unsigned long *);

	struct nvkm_event uevent; /* async user trigger */

	struct nvkm_event cevent; /* channel creation event */

};



struct nvkm_fifo_func {

	void *(*dtor)(struct nvkm_fifo *);

	const struct nvkm_fifo_chan_oclass *chan[];

};

void nvkm_fifo_pause(struct nvkm_fifo *, unsigned long *);

void nvkm_fifo_start(struct nvkm_fifo *, unsigned long *);



void nvkm_fifo_chan_put(struct nvkm_fifo *, unsigned long flags,

			struct nvkm_fifo_chan **);
@@ -81,38 +54,16 @@ nvkm_fifo_chan_inst(struct nvkm_fifo *, u64 inst, unsigned long *flags); 
struct nvkm_fifo_chan *

nvkm_fifo_chan_chid(struct nvkm_fifo *, int chid, unsigned long *flags);



#define nvkm_fifo_create(o,e,c,fc,lc,d)                                     \

	nvkm_fifo_create_((o), (e), (c), (fc), (lc), sizeof(**d), (void **)d)

#define nvkm_fifo_init(p)                                                   \

	nvkm_engine_init_old(&(p)->engine)

#define nvkm_fifo_fini(p,s)                                                 \

	nvkm_engine_fini_old(&(p)->engine, (s))



int nvkm_fifo_create_(struct nvkm_object *, struct nvkm_object *,

			 struct nvkm_oclass *, int min, int max,

			 int size, void **);

void nvkm_fifo_destroy(struct nvkm_fifo *);



#define _nvkm_fifo_init _nvkm_engine_init

#define _nvkm_fifo_fini _nvkm_engine_fini



extern struct nvkm_oclass *nv04_fifo_oclass;

extern struct nvkm_oclass *nv10_fifo_oclass;

extern struct nvkm_oclass *nv17_fifo_oclass;

extern struct nvkm_oclass *nv40_fifo_oclass;

extern struct nvkm_oclass *nv50_fifo_oclass;

extern struct nvkm_oclass *g84_fifo_oclass;

extern struct nvkm_oclass *gf100_fifo_oclass;

extern struct nvkm_oclass *gk104_fifo_oclass;

extern struct nvkm_oclass *gk20a_fifo_oclass;

extern struct nvkm_oclass *gk208_fifo_oclass;

extern struct nvkm_oclass *gm204_fifo_oclass;

extern struct nvkm_oclass *gm20b_fifo_oclass;



int  nvkm_fifo_uevent_ctor(struct nvkm_object *, void *, u32,

			   struct nvkm_notify *);

void nvkm_fifo_uevent(struct nvkm_fifo *);



void nv04_fifo_intr(struct nvkm_subdev *);

int  nv04_fifo_context_attach(struct nvkm_object *, struct nvkm_object *);

int nv04_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);

int nv10_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);

int nv17_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);

int nv40_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);

int nv50_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);

int g84_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);

int gf100_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);

int gk104_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);

int gk208_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);

int gk20a_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);

int gm204_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);

int gm20b_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);

#endif

drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c

+1 −1
Original line number Diff line number Diff line
@@ -231,7 +231,7 @@ nvkm_gpuobj_destroy(struct nvkm_gpuobj *gpuobj) 
	nvkm_object_destroy(&gpuobj->object);

}



#include <engine/fifo.h>

#include <engine/fifo/chan.h>



int

nvkm_gpuobj_create_(struct nvkm_object *parent, struct nvkm_object *engine,

drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c

+1 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 


#include <core/client.h>

#include <core/enum.h>

#include <core/gpuobj.h>

#include <engine/fifo.h>



#include <nvif/class.h>

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

+68 −68
Original line number Diff line number Diff line
@@ -88,7 +88,7 @@ nv4_chipset = { 
	.timer = nv04_timer_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv04_fifo_new,

	.fifo = nv04_fifo_new,

//	.gr = nv04_gr_new,

//	.sw = nv04_sw_new,

};
@@ -108,7 +108,7 @@ nv5_chipset = { 
	.timer = nv04_timer_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv04_fifo_new,

	.fifo = nv04_fifo_new,

//	.gr = nv04_gr_new,

//	.sw = nv04_sw_new,

};
@@ -148,7 +148,7 @@ nv11_chipset = { 
	.timer = nv04_timer_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv10_fifo_new,

	.fifo = nv10_fifo_new,

//	.gr = nv10_gr_new,

//	.sw = nv10_sw_new,

};
@@ -169,7 +169,7 @@ nv15_chipset = { 
	.timer = nv04_timer_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv10_fifo_new,

	.fifo = nv10_fifo_new,

//	.gr = nv10_gr_new,

//	.sw = nv10_sw_new,

};
@@ -190,7 +190,7 @@ nv17_chipset = { 
	.timer = nv04_timer_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

	.fifo = nv17_fifo_new,

//	.gr = nv10_gr_new,

//	.sw = nv10_sw_new,

};
@@ -211,7 +211,7 @@ nv18_chipset = { 
	.timer = nv04_timer_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

	.fifo = nv17_fifo_new,

//	.gr = nv10_gr_new,

//	.sw = nv10_sw_new,

};
@@ -232,7 +232,7 @@ nv1a_chipset = { 
	.timer = nv04_timer_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv10_fifo_new,

	.fifo = nv10_fifo_new,

//	.gr = nv10_gr_new,

//	.sw = nv10_sw_new,

};
@@ -253,7 +253,7 @@ nv1f_chipset = { 
	.timer = nv04_timer_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

	.fifo = nv17_fifo_new,

//	.gr = nv10_gr_new,

//	.sw = nv10_sw_new,

};
@@ -274,7 +274,7 @@ nv20_chipset = { 
	.timer = nv04_timer_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

	.fifo = nv17_fifo_new,

//	.gr = nv20_gr_new,

//	.sw = nv10_sw_new,

};
@@ -295,7 +295,7 @@ nv25_chipset = { 
	.timer = nv04_timer_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

	.fifo = nv17_fifo_new,

//	.gr = nv25_gr_new,

//	.sw = nv10_sw_new,

};
@@ -316,7 +316,7 @@ nv28_chipset = { 
	.timer = nv04_timer_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

	.fifo = nv17_fifo_new,

//	.gr = nv25_gr_new,

//	.sw = nv10_sw_new,

};
@@ -337,7 +337,7 @@ nv2a_chipset = { 
	.timer = nv04_timer_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

	.fifo = nv17_fifo_new,

//	.gr = nv2a_gr_new,

//	.sw = nv10_sw_new,

};
@@ -358,7 +358,7 @@ nv30_chipset = { 
	.timer = nv04_timer_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

	.fifo = nv17_fifo_new,

//	.gr = nv30_gr_new,

//	.sw = nv10_sw_new,

};
@@ -379,7 +379,7 @@ nv31_chipset = { 
	.timer = nv04_timer_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

	.fifo = nv17_fifo_new,

//	.gr = nv30_gr_new,

//	.mpeg = nv31_mpeg_new,

//	.sw = nv10_sw_new,
@@ -401,7 +401,7 @@ nv34_chipset = { 
	.timer = nv04_timer_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

	.fifo = nv17_fifo_new,

//	.gr = nv34_gr_new,

//	.mpeg = nv31_mpeg_new,

//	.sw = nv10_sw_new,
@@ -423,7 +423,7 @@ nv35_chipset = { 
	.timer = nv04_timer_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

	.fifo = nv17_fifo_new,

//	.gr = nv35_gr_new,

//	.sw = nv10_sw_new,

};
@@ -444,7 +444,7 @@ nv36_chipset = { 
	.timer = nv04_timer_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv17_fifo_new,

	.fifo = nv17_fifo_new,

//	.gr = nv35_gr_new,

//	.mpeg = nv31_mpeg_new,

//	.sw = nv10_sw_new,
@@ -468,7 +468,7 @@ nv40_chipset = { 
	.volt = nv40_volt_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv40_mpeg_new,

//	.pm = nv40_pm_new,
@@ -493,7 +493,7 @@ nv41_chipset = { 
	.volt = nv40_volt_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv40_mpeg_new,

//	.pm = nv40_pm_new,
@@ -518,7 +518,7 @@ nv42_chipset = { 
	.volt = nv40_volt_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv40_mpeg_new,

//	.pm = nv40_pm_new,
@@ -543,7 +543,7 @@ nv43_chipset = { 
	.volt = nv40_volt_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv40_mpeg_new,

//	.pm = nv40_pm_new,
@@ -568,7 +568,7 @@ nv44_chipset = { 
	.volt = nv40_volt_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,

//	.pm = nv40_pm_new,
@@ -593,7 +593,7 @@ nv45_chipset = { 
	.volt = nv40_volt_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,

//	.pm = nv40_pm_new,
@@ -618,7 +618,7 @@ nv46_chipset = { 
	.volt = nv40_volt_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,

//	.pm = nv40_pm_new,
@@ -643,7 +643,7 @@ nv47_chipset = { 
	.volt = nv40_volt_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,

//	.pm = nv40_pm_new,
@@ -668,7 +668,7 @@ nv49_chipset = { 
	.volt = nv40_volt_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,

//	.pm = nv40_pm_new,
@@ -693,7 +693,7 @@ nv4a_chipset = { 
	.volt = nv40_volt_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,

//	.pm = nv40_pm_new,
@@ -718,7 +718,7 @@ nv4b_chipset = { 
	.volt = nv40_volt_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,

//	.pm = nv40_pm_new,
@@ -743,7 +743,7 @@ nv4c_chipset = { 
	.volt = nv40_volt_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,

//	.pm = nv40_pm_new,
@@ -768,7 +768,7 @@ nv4e_chipset = { 
	.volt = nv40_volt_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,

//	.pm = nv40_pm_new,
@@ -796,7 +796,7 @@ nv50_chipset = { 
	.volt = nv40_volt_new,

	.disp = nv50_disp_new,

	.dma = nv50_dma_new,

//	.fifo = nv50_fifo_new,

	.fifo = nv50_fifo_new,

//	.gr = nv50_gr_new,

//	.mpeg = nv50_mpeg_new,

//	.pm = nv50_pm_new,
@@ -821,7 +821,7 @@ nv63_chipset = { 
	.volt = nv40_volt_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,

//	.pm = nv40_pm_new,
@@ -846,7 +846,7 @@ nv67_chipset = { 
	.volt = nv40_volt_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,

//	.pm = nv40_pm_new,
@@ -871,7 +871,7 @@ nv68_chipset = { 
	.volt = nv40_volt_new,

	.disp = nv04_disp_new,

	.dma = nv04_dma_new,

//	.fifo = nv40_fifo_new,

	.fifo = nv40_fifo_new,

//	.gr = nv40_gr_new,

//	.mpeg = nv44_mpeg_new,

//	.pm = nv40_pm_new,
@@ -901,7 +901,7 @@ nv84_chipset = { 
	.cipher = g84_cipher_new,

	.disp = g84_disp_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

//	.mpeg = g84_mpeg_new,

//	.pm = g84_pm_new,
@@ -932,7 +932,7 @@ nv86_chipset = { 
	.cipher = g84_cipher_new,

	.disp = g84_disp_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

//	.mpeg = g84_mpeg_new,

//	.pm = g84_pm_new,
@@ -963,7 +963,7 @@ nv92_chipset = { 
	.cipher = g84_cipher_new,

	.disp = g84_disp_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

//	.mpeg = g84_mpeg_new,

//	.pm = g84_pm_new,
@@ -994,7 +994,7 @@ nv94_chipset = { 
	.cipher = g84_cipher_new,

	.disp = g94_disp_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

//	.mpeg = g84_mpeg_new,

//	.pm = g84_pm_new,
@@ -1022,7 +1022,7 @@ nv96_chipset = { 
	.bar = g84_bar_new,

	.volt = nv40_volt_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

	.fifo = g84_fifo_new,

//	.sw = nv50_sw_new,

//	.gr = nv50_gr_new,

//	.mpeg = g84_mpeg_new,
@@ -1053,7 +1053,7 @@ nv98_chipset = { 
	.bar = g84_bar_new,

	.volt = nv40_volt_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

	.fifo = g84_fifo_new,

//	.sw = nv50_sw_new,

//	.gr = nv50_gr_new,

	.mspdec = g98_mspdec_new,
@@ -1087,7 +1087,7 @@ nva0_chipset = { 
	.cipher = g84_cipher_new,

	.disp = gt200_disp_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

//	.mpeg = g84_mpeg_new,

//	.pm = gt200_pm_new,
@@ -1118,7 +1118,7 @@ nva3_chipset = { 
	.ce[0] = gt215_ce_new,

	.disp = gt215_disp_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

//	.mpeg = g84_mpeg_new,

	.mspdec = gt215_mspdec_new,
@@ -1151,7 +1151,7 @@ nva5_chipset = { 
	.ce[0] = gt215_ce_new,

	.disp = gt215_disp_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

	.mspdec = gt215_mspdec_new,

	.msppp = gt215_msppp_new,
@@ -1183,7 +1183,7 @@ nva8_chipset = { 
	.ce[0] = gt215_ce_new,

	.disp = gt215_disp_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

	.mspdec = gt215_mspdec_new,

	.msppp = gt215_msppp_new,
@@ -1213,7 +1213,7 @@ nvaa_chipset = { 
	.volt = nv40_volt_new,

	.disp = g94_disp_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

	.mspdec = g98_mspdec_new,

	.msppp = g98_msppp_new,
@@ -1244,7 +1244,7 @@ nvac_chipset = { 
	.volt = nv40_volt_new,

	.disp = g94_disp_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

	.mspdec = g98_mspdec_new,

	.msppp = g98_msppp_new,
@@ -1277,7 +1277,7 @@ nvaf_chipset = { 
	.ce[0] = gt215_ce_new,

	.disp = gt215_disp_new,

	.dma = nv50_dma_new,

//	.fifo = g84_fifo_new,

	.fifo = g84_fifo_new,

//	.gr = nv50_gr_new,

	.mspdec = gt215_mspdec_new,

	.msppp = gt215_msppp_new,
@@ -1312,7 +1312,7 @@ nvc0_chipset = { 
	.ce[1] = gf100_ce_new,

	.disp = gt215_disp_new,

	.dma = gf100_dma_new,

//	.fifo = gf100_fifo_new,

	.fifo = gf100_fifo_new,

//	.gr = gf100_gr_new,

	.mspdec = gf100_mspdec_new,

	.msppp = gf100_msppp_new,
@@ -1346,7 +1346,7 @@ nvc1_chipset = { 
	.ce[0] = gf100_ce_new,

	.disp = gt215_disp_new,

	.dma = gf100_dma_new,

//	.fifo = gf100_fifo_new,

	.fifo = gf100_fifo_new,

//	.gr = gf108_gr_new,

	.mspdec = gf100_mspdec_new,

	.msppp = gf100_msppp_new,
@@ -1380,7 +1380,7 @@ nvc3_chipset = { 
	.ce[0] = gf100_ce_new,

	.disp = gt215_disp_new,

	.dma = gf100_dma_new,

//	.fifo = gf100_fifo_new,

	.fifo = gf100_fifo_new,

//	.gr = gf104_gr_new,

	.mspdec = gf100_mspdec_new,

	.msppp = gf100_msppp_new,
@@ -1415,7 +1415,7 @@ nvc4_chipset = { 
	.ce[1] = gf100_ce_new,

	.disp = gt215_disp_new,

	.dma = gf100_dma_new,

//	.fifo = gf100_fifo_new,

	.fifo = gf100_fifo_new,

//	.gr = gf104_gr_new,

	.mspdec = gf100_mspdec_new,

	.msppp = gf100_msppp_new,
@@ -1450,7 +1450,7 @@ nvc8_chipset = { 
	.ce[1] = gf100_ce_new,

	.disp = gt215_disp_new,

	.dma = gf100_dma_new,

//	.fifo = gf100_fifo_new,

	.fifo = gf100_fifo_new,

//	.gr = gf110_gr_new,

	.mspdec = gf100_mspdec_new,

	.msppp = gf100_msppp_new,
@@ -1485,7 +1485,7 @@ nvce_chipset = { 
	.ce[1] = gf100_ce_new,

	.disp = gt215_disp_new,

	.dma = gf100_dma_new,

//	.fifo = gf100_fifo_new,

	.fifo = gf100_fifo_new,

//	.gr = gf104_gr_new,

	.mspdec = gf100_mspdec_new,

	.msppp = gf100_msppp_new,
@@ -1519,7 +1519,7 @@ nvcf_chipset = { 
	.ce[0] = gf100_ce_new,

	.disp = gt215_disp_new,

	.dma = gf100_dma_new,

//	.fifo = gf100_fifo_new,

	.fifo = gf100_fifo_new,

//	.gr = gf104_gr_new,

	.mspdec = gf100_mspdec_new,

	.msppp = gf100_msppp_new,
@@ -1551,7 +1551,7 @@ nvd7_chipset = { 
	.ce[0] = gf100_ce_new,

	.disp = gf119_disp_new,

	.dma = gf119_dma_new,

//	.fifo = gf100_fifo_new,

	.fifo = gf100_fifo_new,

//	.gr = gf117_gr_new,

	.mspdec = gf100_mspdec_new,

	.msppp = gf100_msppp_new,
@@ -1585,7 +1585,7 @@ nvd9_chipset = { 
	.ce[0] = gf100_ce_new,

	.disp = gf119_disp_new,

	.dma = gf119_dma_new,

//	.fifo = gf100_fifo_new,

	.fifo = gf100_fifo_new,

//	.gr = gf119_gr_new,

	.mspdec = gf100_mspdec_new,

	.msppp = gf100_msppp_new,
@@ -1621,7 +1621,7 @@ nve4_chipset = { 
	.ce[2] = gk104_ce_new,

	.disp = gk104_disp_new,

	.dma = gf119_dma_new,

//	.fifo = gk104_fifo_new,

	.fifo = gk104_fifo_new,

//	.gr = gk104_gr_new,

	.mspdec = gk104_mspdec_new,

	.msppp = gf100_msppp_new,
@@ -1657,7 +1657,7 @@ nve6_chipset = { 
	.ce[2] = gk104_ce_new,

	.disp = gk104_disp_new,

	.dma = gf119_dma_new,

//	.fifo = gk104_fifo_new,

	.fifo = gk104_fifo_new,

//	.gr = gk104_gr_new,

	.mspdec = gk104_mspdec_new,

	.msppp = gf100_msppp_new,
@@ -1693,7 +1693,7 @@ nve7_chipset = { 
	.ce[2] = gk104_ce_new,

	.disp = gk104_disp_new,

	.dma = gf119_dma_new,

//	.fifo = gk104_fifo_new,

	.fifo = gk104_fifo_new,

//	.gr = gk104_gr_new,

	.mspdec = gk104_mspdec_new,

	.msppp = gf100_msppp_new,
@@ -1720,7 +1720,7 @@ nvea_chipset = { 
	.volt = gk20a_volt_new,

	.ce[2] = gk104_ce_new,

	.dma = gf119_dma_new,

//	.fifo = gk20a_fifo_new,

	.fifo = gk20a_fifo_new,

//	.gr = gk20a_gr_new,

//	.pm = gk104_pm_new,

//	.sw = gf100_sw_new,
@@ -1753,7 +1753,7 @@ nvf0_chipset = { 
	.ce[2] = gk104_ce_new,

	.disp = gk110_disp_new,

	.dma = gf119_dma_new,

//	.fifo = gk104_fifo_new,

	.fifo = gk104_fifo_new,

//	.gr = gk110_gr_new,

	.mspdec = gk104_mspdec_new,

	.msppp = gf100_msppp_new,
@@ -1789,7 +1789,7 @@ nvf1_chipset = { 
	.ce[2] = gk104_ce_new,

	.disp = gk110_disp_new,

	.dma = gf119_dma_new,

//	.fifo = gk104_fifo_new,

	.fifo = gk104_fifo_new,

//	.gr = gk110b_gr_new,

	.mspdec = gk104_mspdec_new,

	.msppp = gf100_msppp_new,
@@ -1825,7 +1825,7 @@ nv106_chipset = { 
	.ce[2] = gk104_ce_new,

	.disp = gk110_disp_new,

	.dma = gf119_dma_new,

//	.fifo = gk208_fifo_new,

	.fifo = gk208_fifo_new,

//	.gr = gk208_gr_new,

	.mspdec = gk104_mspdec_new,

	.msppp = gf100_msppp_new,
@@ -1860,7 +1860,7 @@ nv108_chipset = { 
	.ce[2] = gk104_ce_new,

	.disp = gk110_disp_new,

	.dma = gf119_dma_new,

//	.fifo = gk208_fifo_new,

	.fifo = gk208_fifo_new,

//	.gr = gk208_gr_new,

	.mspdec = gk104_mspdec_new,

	.msppp = gf100_msppp_new,
@@ -1893,7 +1893,7 @@ nv117_chipset = { 
	.ce[2] = gk104_ce_new,

	.disp = gm107_disp_new,

	.dma = gf119_dma_new,

//	.fifo = gk208_fifo_new,

	.fifo = gk208_fifo_new,

//	.gr = gm107_gr_new,

//	.sw = gf100_sw_new,

};
@@ -1922,7 +1922,7 @@ nv124_chipset = { 
	.ce[2] = gm204_ce_new,

	.disp = gm204_disp_new,

	.dma = gf119_dma_new,

//	.fifo = gm204_fifo_new,

	.fifo = gm204_fifo_new,

//	.gr = gm204_gr_new,

//	.sw = gf100_sw_new,

};
@@ -1951,7 +1951,7 @@ nv126_chipset = { 
	.ce[2] = gm204_ce_new,

	.disp = gm204_disp_new,

	.dma = gf119_dma_new,

//	.fifo = gm204_fifo_new,

	.fifo = gm204_fifo_new,

//	.gr = gm206_gr_new,

//	.sw = gf100_sw_new,

};
@@ -1972,7 +1972,7 @@ nv12b_chipset = { 
	.timer = gk20a_timer_new,

	.ce[2] = gm204_ce_new,

	.dma = gf119_dma_new,

//	.fifo = gm20b_fifo_new,

	.fifo = gm20b_fifo_new,

//	.gr = gm20b_gr_new,

//	.sw = gf100_sw_new,

};

drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c

+0 −9
Original line number Diff line number Diff line
@@ -28,55 +28,46 @@ gf100_identify(struct nvkm_device *device) 
{

	switch (device->chipset) {

	case 0xc0:

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf100_gr_oclass;

		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;

		break;

	case 0xc4:

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;

		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;

		break;

	case 0xc3:

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;

		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;

		break;

	case 0xce:

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;

		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;

		break;

	case 0xcf:

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;

		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;

		break;

	case 0xc1:

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf108_gr_oclass;

		device->oclass[NVDEV_ENGINE_PM     ] = gf108_pm_oclass;

		break;

	case 0xc8:

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf110_gr_oclass;

		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;

		break;

	case 0xd9:

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf119_gr_oclass;

		device->oclass[NVDEV_ENGINE_PM     ] = gf117_pm_oclass;

		break;

	case 0xd7:

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gf117_gr_oclass;

		device->oclass[NVDEV_ENGINE_PM     ] = gf117_pm_oclass;