Commit 141f66eb authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Rob Clark
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drm/msm/a5xx: fix highest bank bit for a530 



A530 has highest bank bit equal to 15 (like A540). Fix values written to
REG_A5XX_RB_MODE_CNTL and REG_A5XX_TPL1_MODE_CNTL registers.

Fixes: 1d832ab3 ("drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs")
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/522639/
Link: https://lore.kernel.org/r/20230214020956.164473-3-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent a7a4c19c

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+1 −1
Original line number Diff line number Diff line
@@ -806,7 +806,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu) 
	gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F);



	/* Set the highest bank bit */

	if (adreno_is_a540(adreno_gpu))

	if (adreno_is_a540(adreno_gpu) || adreno_is_a530(adreno_gpu))

		regbit = 2;

	else

		regbit = 1;