Commit 141fbc27 authored by Neil Armstrong's avatar Neil Armstrong Committed by Jerome Brunet
Browse files

clk: meson: migrate meson-eeclk out of hw_onecell_data to drop NR_CLKS 



The way hw_onecell_data is declared:
      struct clk_hw_onecell_data {
              unsigned int num;
              struct clk_hw *hws[];
      };

makes it impossible to have the clk_hw table declared outside while
using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible
array member.

Completely move out of hw_onecell_data and add a custom
devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw
from the meson_eeclkc_data struct to finally get rid on the
NR_CLKS define.

Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-2-38172d17c27a@linaro.org


Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 230b6f3a

drivers/clk/meson/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ config COMMON_CLK_MESON_AO_CLKC 
config COMMON_CLK_MESON_EE_CLKC

	tristate

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_CLKC_UTILS



config COMMON_CLK_MESON_CPU_DYNDIV

	tristate

drivers/clk/meson/axg.c

+141 −142
Original line number Diff line number Diff line
@@ -1890,8 +1890,7 @@ static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4); 


/* Array of all clocks provided by this provider */



static struct clk_hw_onecell_data axg_hw_onecell_data = {

	.hws = {

static struct clk_hw *axg_hw_clks[] = {

	[CLKID_SYS_PLL]			= &axg_sys_pll.hw,

	[CLKID_FIXED_PLL]		= &axg_fixed_pll.hw,

	[CLKID_FCLK_DIV2]		= &axg_fclk_div2.hw,
@@ -2028,9 +2027,6 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = { 
	[CLKID_VDIN_MEAS_SEL]		= &axg_vdin_meas_sel.hw,

	[CLKID_VDIN_MEAS_DIV]		= &axg_vdin_meas_div.hw,

	[CLKID_VDIN_MEAS]		= &axg_vdin_meas.hw,

		[NR_CLKS]			= NULL,

	},

	.num = NR_CLKS,

};



/* Convenience table to populate regmap in .probe */
@@ -2163,7 +2159,10 @@ static struct clk_regmap *const axg_clk_regmaps[] = { 
static const struct meson_eeclkc_data axg_clkc_data = {

	.regmap_clks = axg_clk_regmaps,

	.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),

	.hw_onecell_data = &axg_hw_onecell_data,

	.hw_clks = {

		.hws = axg_hw_clks,

		.num = ARRAY_SIZE(axg_hw_clks),

	},

};

drivers/clk/meson/axg.h

+0 −2
Original line number Diff line number Diff line
@@ -160,8 +160,6 @@ 
#define CLKID_VDIN_MEAS_SEL			134

#define CLKID_VDIN_MEAS_DIV			135



#define NR_CLKS					137



/* include the CLKIDs that have been made part of the DT binding */

#include <dt-bindings/clock/axg-clkc.h>

drivers/clk/meson/g12a.c

+742 −745
Original line number Diff line number Diff line
@@ -4244,8 +4244,7 @@ static MESON_GATE_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3); 
static MESON_GATE_RO(g12a_sec_ahb_apb3,		HHI_GCLK_OTHER2, 4);



/* Array of all clocks provided by this provider */

static struct clk_hw_onecell_data g12a_hw_onecell_data = {

	.hws = {

static struct clk_hw *g12a_hw_clks[] = {

	[CLKID_SYS_PLL]			= &g12a_sys_pll.hw,

	[CLKID_FIXED_PLL]		= &g12a_fixed_pll.hw,

	[CLKID_FCLK_DIV2]		= &g12a_fclk_div2.hw,
@@ -4468,13 +4467,9 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { 
	[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,

	[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,

	[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,

		[NR_CLKS]			= NULL,

	},

	.num = NR_CLKS,

};



static struct clk_hw_onecell_data g12b_hw_onecell_data = {

	.hws = {

static struct clk_hw *g12b_hw_clks[] = {

	[CLKID_SYS_PLL]			= &g12a_sys_pll.hw,

	[CLKID_FIXED_PLL]		= &g12a_fixed_pll.hw,

	[CLKID_FCLK_DIV2]		= &g12a_fclk_div2.hw,
@@ -4732,13 +4727,9 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = { 
	[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,

	[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,

	[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,

		[NR_CLKS]			= NULL,

	},

	.num = NR_CLKS,

};



static struct clk_hw_onecell_data sm1_hw_onecell_data = {

	.hws = {

static struct clk_hw *sm1_hw_clks[] = {

	[CLKID_SYS_PLL]			= &g12a_sys_pll.hw,

	[CLKID_FIXED_PLL]		= &g12a_fixed_pll.hw,

	[CLKID_FCLK_DIV2]		= &g12a_fclk_div2.hw,
@@ -4981,9 +4972,6 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = { 
	[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,

	[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,

	[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,

		[NR_CLKS]			= NULL,

	},

	.num = NR_CLKS,

};



/* Convenience table to populate regmap in .probe */
@@ -5274,7 +5262,7 @@ static int meson_g12a_dvfs_setup_common(struct device *dev, 


static int meson_g12b_dvfs_setup(struct platform_device *pdev)

{

	struct clk_hw **hws = g12b_hw_onecell_data.hws;

	struct clk_hw **hws = g12b_hw_clks;

	struct device *dev = &pdev->dev;

	struct clk *notifier_clk;

	struct clk_hw *xtal;
@@ -5351,7 +5339,7 @@ static int meson_g12b_dvfs_setup(struct platform_device *pdev) 


static int meson_g12a_dvfs_setup(struct platform_device *pdev)

{

	struct clk_hw **hws = g12a_hw_onecell_data.hws;

	struct clk_hw **hws = g12a_hw_clks;

	struct device *dev = &pdev->dev;

	struct clk *notifier_clk;

	int ret;
@@ -5413,7 +5401,10 @@ static const struct meson_g12a_data g12a_clkc_data = { 
	.eeclkc_data = {

		.regmap_clks = g12a_clk_regmaps,

		.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),

		.hw_onecell_data = &g12a_hw_onecell_data,

		.hw_clks = {

			.hws = g12a_hw_clks,

			.num = ARRAY_SIZE(g12a_hw_clks),

		},

		.init_regs = g12a_init_regs,

		.init_count = ARRAY_SIZE(g12a_init_regs),

	},
@@ -5424,7 +5415,10 @@ static const struct meson_g12a_data g12b_clkc_data = { 
	.eeclkc_data = {

		.regmap_clks = g12a_clk_regmaps,

		.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),

		.hw_onecell_data = &g12b_hw_onecell_data,

		.hw_clks = {

			.hws = g12b_hw_clks,

			.num = ARRAY_SIZE(g12b_hw_clks),

		},

	},

	.dvfs_setup = meson_g12b_dvfs_setup,

};
@@ -5433,7 +5427,10 @@ static const struct meson_g12a_data sm1_clkc_data = { 
	.eeclkc_data = {

		.regmap_clks = g12a_clk_regmaps,

		.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),

		.hw_onecell_data = &sm1_hw_onecell_data,

		.hw_clks = {

			.hws = sm1_hw_clks,

			.num = ARRAY_SIZE(sm1_hw_clks),

		},

	},

	.dvfs_setup = meson_g12a_dvfs_setup,

};

drivers/clk/meson/g12a.h

+0 −2
Original line number Diff line number Diff line
@@ -266,8 +266,6 @@ 
#define CLKID_NNA_CORE_CLK_DIV			266

#define CLKID_MIPI_DSI_PXCLK_DIV		268



#define NR_CLKS					271



/* include the CLKIDs that have been made part of the DT binding */

#include <dt-bindings/clock/g12a-clkc.h>