Commit 14ad1529 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Make skl+ universal plane registers unlocked 



Drop the locks around most universal plane register writes.
The lock isn't needed since each plane's register are neatly
contained on their own cachelines.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220210062403.18690-3-ville.syrjala@linux.intel.com


Reviewed-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
parent f8a005eb

drivers/gpu/drm/i915/display/skl_universal_plane.c

+0 −35
Original line number Diff line number Diff line
@@ -615,16 +615,11 @@ skl_plane_disable_arm(struct intel_plane *plane, 
	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	enum plane_id plane_id = plane->id;

	enum pipe pipe = plane->pipe;

	unsigned long irqflags;



	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);



	skl_write_plane_wm(plane, crtc_state);



	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);

	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);



	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}



static void
@@ -634,9 +629,6 @@ icl_plane_disable_arm(struct intel_plane *plane, 
	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	enum plane_id plane_id = plane->id;

	enum pipe pipe = plane->pipe;

	unsigned long irqflags;



	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);



	if (icl_is_hdr_plane(dev_priv, plane_id))

		intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0);
@@ -646,8 +638,6 @@ icl_plane_disable_arm(struct intel_plane *plane, 
	intel_psr2_disable_plane_sel_fetch(plane, crtc_state);

	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);

	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);



	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}



static bool
@@ -1108,7 +1098,6 @@ skl_plane_update_noarm(struct intel_plane *plane, 
	int crtc_y = plane_state->uapi.dst.y1;

	u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

	u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

	unsigned long irqflags;



	/* The scaler will handle the output position */

	if (plane_state->scaler_id >= 0) {
@@ -1116,8 +1105,6 @@ skl_plane_update_noarm(struct intel_plane *plane, 
		crtc_y = 0;

	}



	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);



	intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),

			  PLANE_STRIDE_(stride));

	intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
@@ -1126,8 +1113,6 @@ skl_plane_update_noarm(struct intel_plane *plane, 
			  PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));



	skl_write_plane_wm(plane, crtc_state);



	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}



static void
@@ -1141,7 +1126,6 @@ skl_plane_update_arm(struct intel_plane *plane, 
	u32 x = plane_state->view.color_plane[0].x;

	u32 y = plane_state->view.color_plane[0].y;

	u32 plane_ctl, plane_color_ctl = 0;

	unsigned long irqflags;



	plane_ctl = plane_state->ctl |

		skl_plane_ctl_crtc(crtc_state);
@@ -1150,8 +1134,6 @@ skl_plane_update_arm(struct intel_plane *plane, 
		plane_color_ctl = plane_state->color_ctl |

			glk_plane_color_ctl_crtc(crtc_state);



	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);



	intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state));

	intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state));

	intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state));
@@ -1187,8 +1169,6 @@ skl_plane_update_arm(struct intel_plane *plane, 
	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);

	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),

			  skl_plane_surf(plane_state, 0));



	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}



static void
@@ -1209,7 +1189,6 @@ icl_plane_update_noarm(struct intel_plane *plane, 
	int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;

	int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;

	u32 plane_color_ctl;

	unsigned long irqflags;



	plane_color_ctl = plane_state->color_ctl |

		glk_plane_color_ctl_crtc(crtc_state);
@@ -1220,8 +1199,6 @@ icl_plane_update_noarm(struct intel_plane *plane, 
		crtc_y = 0;

	}



	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);



	intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),

			  PLANE_STRIDE_(stride));

	intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
@@ -1265,8 +1242,6 @@ icl_plane_update_noarm(struct intel_plane *plane, 
		icl_plane_csc_load_black(plane);



	intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);



	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}



static void
@@ -1279,13 +1254,10 @@ icl_plane_update_arm(struct intel_plane *plane, 
	enum pipe pipe = plane->pipe;

	int color_plane = icl_plane_color_plane(plane_state);

	u32 plane_ctl;

	unsigned long irqflags;



	plane_ctl = plane_state->ctl |

		skl_plane_ctl_crtc(crtc_state);



	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);



	/*

	 * Enable the scaler before the plane so that we don't

	 * get a catastrophic underrun even if the two operations
@@ -1304,8 +1276,6 @@ icl_plane_update_arm(struct intel_plane *plane, 
	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);

	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),

			  skl_plane_surf(plane_state, color_plane));



	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}



static void
@@ -1315,7 +1285,6 @@ skl_plane_async_flip(struct intel_plane *plane, 
		     bool async_flip)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	unsigned long irqflags;

	enum plane_id plane_id = plane->id;

	enum pipe pipe = plane->pipe;

	u32 plane_ctl = plane_state->ctl;
@@ -1325,13 +1294,9 @@ skl_plane_async_flip(struct intel_plane *plane, 
	if (async_flip)

		plane_ctl |= PLANE_CTL_ASYNC_FLIP;



	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);



	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);

	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),

			  skl_plane_surf(plane_state, 0));



	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

}



static bool intel_format_is_p01x(u32 format)