Commit 14e1eb5a authored by Florian Fainelli's avatar Florian Fainelli
Browse files

dt-bindings: arm: Document Broadcom SoCs 'secondary-boot-reg' 



Consolidate and move the 'secondary-boot-reg' property from the 3
existing binding documents into the main cpus.yaml documentation, also
make sure that the property is enforced when relevant.

Acked-by: default avatarMaxime Ripard <mripard@kernel.org>
Acked-by: default avatarScott Branden <scott.branden@broadcom.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
parent b63b50ab

Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt

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Broadcom Kona Family CPU Enable Method

--------------------------------------

This binding defines the enable method used for starting secondary

CPUs in the following Broadcom SoCs:

  BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664



The enable method is specified by defining the following required

properties in the "cpu" device tree node:

  - enable-method = "brcm,bcm11351-cpu-method";

  - secondary-boot-reg = <...>;



The secondary-boot-reg property is a u32 value that specifies the

physical address of the register used to request the ROM holding pen

code release a secondary CPU.  The value written to the register is

formed by encoding the target CPU id into the low bits of the

physical start address it should jump to.



Example:

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <1>;

			enable-method = "brcm,bcm11351-cpu-method";

			secondary-boot-reg = <0x3500417c>;

		};

	};

Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt

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Broadcom Kona Family CPU Enable Method

--------------------------------------

This binding defines the enable method used for starting secondary

CPUs in the following Broadcom SoCs:

  BCM23550



The enable method is specified by defining the following required

properties in the "cpu" device tree node:

  - enable-method = "brcm,bcm23550";

  - secondary-boot-reg = <...>;



The secondary-boot-reg property is a u32 value that specifies the

physical address of the register used to request the ROM holding pen

code release a secondary CPU.  The value written to the register is

formed by encoding the target CPU id into the low bits of the

physical start address it should jump to.



Example:

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <1>;

			enable-method = "brcm,bcm23550";

			secondary-boot-reg = <0x3500417c>;

		};

	};

Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt

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Broadcom Northstar Plus SoC CPU Enable Method

---------------------------------------------

This binding defines the enable method used for starting secondary

CPU in the following Broadcom SoCs:

  BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312



The enable method is specified by defining the following required

properties in the corresponding secondary "cpu" device tree node:

  - enable-method = "brcm,bcm-nsp-smp";

  - secondary-boot-reg = <...>;



The secondary-boot-reg property is a u32 value that specifies the

physical address of the register which should hold the common

entry point for a secondary CPU. This entry is cpu node specific

and should be added per cpu. E.g., in case of NSP (BCM58625) which

is a dual core CPU SoC, this entry should be added to cpu1 node.





Example:

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <0>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			enable-method = "brcm,bcm-nsp-smp";

			secondary-boot-reg = <0xffff042c>;

			reg = <1>;

		};

	};

Documentation/devicetree/bindings/arm/cpus.yaml

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@@ -287,6 +287,39 @@ properties: 
      While optional, it is the preferred way to get access to

      the cpu-core power-domains.



  secondary-boot-reg:

    $ref: '/schemas/types.yaml#/definitions/uint32'

    description: |

      Required for systems that have an "enable-method" property value of

      "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".



      This includes the following SoCs: |

      BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550

      BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312



      The secondary-boot-reg property is a u32 value that specifies the

      physical address of the register used to request the ROM holding pen

      code release a secondary CPU. The value written to the register is

      formed by encoding the target CPU id into the low bits of the

      physical start address it should jump to.



if:

  # If the enable-method property contains one of those values

  properties:

    enable-method:

      contains:

        enum:

          - brcm,bcm11351-cpu-method

          - brcm,bcm23550

          - brcm,bcm-nsp-smp

  # and if enable-method is present

  required:

    - enable-method



then:

   required:

     - secondary-boot-reg



required:

  - device_type

  - reg