Commit 153e3979 authored by Clemens Ladisch's avatar Clemens Ladisch
Browse files

firewire: ohci: speed up PHY register accesses 



Most PHY chips, when idle, can complete a register access in the time
needed for two or three PCI read transactions; bigger delays occur only
when data is currently being moved over the link/PHY interface.  So if
we busy-wait a few times when waiting for the register access to finish,
it is likely that we can finish without having to sleep.

Signed-off-by: default avatarClemens Ladisch <clemens@ladisch.de>
parent f9c70f91

drivers/firewire/ohci.c

+10 −4
Original line number Diff line number Diff line
@@ -474,11 +474,16 @@ static int read_phy_reg(struct fw_ohci *ohci, int addr) 
	int i;



	reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));

	for (i = 0; i < 10; i++) {

	for (i = 0; i < 3 + 100; i++) {

		val = reg_read(ohci, OHCI1394_PhyControl);

		if (val & OHCI1394_PhyControl_ReadDone)

			return OHCI1394_PhyControl_ReadData(val);



		/*

		 * Try a few times without waiting.  Sleeping is necessary

		 * only when the link/PHY interface is busy.

		 */

		if (i >= 3)

			msleep(1);

	}

	fw_error("failed to read phy reg\n");
@@ -492,11 +497,12 @@ static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) 


	reg_write(ohci, OHCI1394_PhyControl,

		  OHCI1394_PhyControl_Write(addr, val));

	for (i = 0; i < 100; i++) {

	for (i = 0; i < 3 + 100; i++) {

		val = reg_read(ohci, OHCI1394_PhyControl);

		if (!(val & OHCI1394_PhyControl_WritePending))

			return 0;



		if (i >= 3)

			msleep(1);

	}

	fw_error("failed to write phy reg\n");