Commit 157e72e8 authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: add sdma ip block for sienna_cichlid (v5) 



Sienna_Cichlid have 4 sdma controllers.

v2: add missing license to sdma_common.h (Alex)
v3: rebase (Alex)
v4: squash in policy fix (Alex)
v4: squash in fw_name fix

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 06ff634c

drivers/gpu/drm/amd/amdgpu/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -129,7 +129,8 @@ amdgpu-y += \ 
	sdma_v2_4.o \

	sdma_v3_0.o \

	sdma_v4_0.o \

	sdma_v5_0.o

	sdma_v5_0.o \

	sdma_v5_2.o



# add MES block

amdgpu-y += \

drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h

+2 −0
Original line number Diff line number Diff line
@@ -180,6 +180,8 @@ typedef enum _AMDGPU_NAVI10_DOORBELL_ASSIGNMENT 
	/* SDMA:256~335*/

	AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0		= 0x100,

	AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1		= 0x10A,

	AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2		= 0x114,

	AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3		= 0x11E,

	/* IH: 376~391 */

	AMDGPU_NAVI10_DOORBELL_IH			= 0x178,

	/* MMSCH: 392~407

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

+7 −1
Original line number Diff line number Diff line
@@ -33,6 +33,10 @@ 
#define smnCPM_CONTROL		0x11180460

#define smnPCIE_CNTL2		0x11180070



#define mmBIF_SDMA2_DOORBELL_RANGE		0x01d6

#define mmBIF_SDMA2_DOORBELL_RANGE_BASE_IDX	2

#define mmBIF_SDMA3_DOORBELL_RANGE		0x01d7

#define mmBIF_SDMA3_DOORBELL_RANGE_BASE_IDX	2



static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev)

{
@@ -81,7 +85,9 @@ static void nbio_v2_3_sdma_doorbell_range(struct amdgpu_device *adev, int instan 
					  int doorbell_size)

{

	u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :

			SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);

			instance == 1 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE) :

			instance == 2 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA2_DOORBELL_RANGE) :

			SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA3_DOORBELL_RANGE);



	u32 doorbell_range = RREG32(reg);

drivers/gpu/drm/amd/amdgpu/nv.c

+4 −0
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ 
#include "navi10_ih.h"

#include "gfx_v10_0.h"

#include "sdma_v5_0.h"

#include "sdma_v5_2.h"

#include "vcn_v2_0.h"

#include "jpeg_v2_0.h"

#include "dce_virtual.h"
@@ -488,6 +489,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) 
		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);

		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);

		break;

	default:

		return -EINVAL;
@@ -566,6 +568,8 @@ static void nv_init_doorbell_index(struct amdgpu_device *adev) 
	adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;

	adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;

	adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;

	adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;

	adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;

	adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;

	adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;

	adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;

drivers/gpu/drm/amd/amdgpu/sdma_common.h

0 → 100644
+42 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2019 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef __SDMA_COMMON_H__

#define __SDMA_COMMON_H__



enum sdma_utcl2_cache_read_policy {

	CACHE_READ_POLICY_L2__LRU    = 0x00000000,

	CACHE_READ_POLICY_L2__STREAM = 0x00000001,

	CACHE_READ_POLICY_L2__NOA    = 0x00000002,

	CACHE_READ_POLICY_L2__DEFAULT = CACHE_READ_POLICY_L2__NOA,

};



enum sdma_utcl2_cache_write_policy {

	CACHE_WRITE_POLICY_L2__LRU    = 0x00000000,

	CACHE_WRITE_POLICY_L2__STREAM = 0x00000001,

	CACHE_WRITE_POLICY_L2__NOA    = 0x00000002,

	CACHE_WRITE_POLICY_L2__BYPASS = 0x00000003,

	CACHE_WRITE_POLICY_L2__DEFAULT = CACHE_WRITE_POLICY_L2__BYPASS,

};



#endif /* __SDMA_COMMON_H__ */