Loading drivers/staging/rtl8192e/r8190P_def.h +36 −36 Original line number Diff line number Diff line Loading @@ -85,7 +85,7 @@ enum rtl819x_loopback { #define BT_QA_BOARD 1 #define BT_FPGA 2 #define Rx_Smooth_Factor 20 #define RX_SMOOTH 20 #define QSLT_BK 0x1 #define QSLT_BE 0x0 Loading drivers/staging/rtl8192e/r8190P_rtl8256.c +120 −66 Original line number Diff line number Diff line Loading @@ -22,7 +22,8 @@ #include "r8192E_phy.h" #include "r8190P_rtl8256.h" void PHY_SetRF8256Bandwidth(struct net_device* dev , enum ht_channel_width Bandwidth) void PHY_SetRF8256Bandwidth(struct net_device *dev, enum ht_channel_width Bandwidth) { u8 eRFPath; struct r8192_priv *priv = rtllib_priv(dev); Loading @@ -33,30 +34,47 @@ void PHY_SetRF8256Bandwidth(struct net_device* dev , enum ht_channel_width Bandw switch (Bandwidth) { case HT_CHANNEL_WIDTH_20: if (priv->card_8192_version == VERSION_8190_BD || priv->card_8192_version == VERSION_8190_BE) { rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0b, bMask12Bits, 0x100); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x2c, bMask12Bits, 0x3d7); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0e, bMask12Bits, 0x021); if (priv->card_8192_version == VERSION_8190_BD || priv->card_8192_version == VERSION_8190_BE) { rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0b, bMask12Bits, 0x100); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x2c, bMask12Bits, 0x3d7); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0e, bMask12Bits, 0x021); } else { RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n"); RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): " "unknown hardware version\n"); } break; case HT_CHANNEL_WIDTH_20_40: if (priv->card_8192_version == VERSION_8190_BD ||priv->card_8192_version == VERSION_8190_BE) { rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0b, bMask12Bits, 0x300); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x2c, bMask12Bits, 0x3ff); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0e, bMask12Bits, 0x0e1); if (priv->card_8192_version == VERSION_8190_BD || priv->card_8192_version == VERSION_8190_BE) { rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0b, bMask12Bits, 0x300); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x2c, bMask12Bits, 0x3ff); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0e, bMask12Bits, 0x0e1); } else { RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n"); RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): " "unknown hardware version\n"); } break; default: RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ); RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown " "Bandwidth: %#X\n", Bandwidth); break; } Loading Loading @@ -87,7 +105,8 @@ bool phy_RF8256_Config_ParaFile(struct net_device* dev) u8 ConstRetryTimes = 5, RetryTimes = 5; u8 ret = 0; for (eRFPath = (enum rf90_radio_path)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++) { for (eRFPath = (enum rf90_radio_path)RF90_PATH_A; eRFPath < priv->NumTotalRFPath; eRFPath++) { if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) continue; Loading @@ -97,11 +116,13 @@ bool phy_RF8256_Config_ParaFile(struct net_device* dev) switch (eRFPath) { case RF90_PATH_A: case RF90_PATH_C: u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV); u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV); break; case RF90_PATH_B: case RF90_PATH_D: u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16); u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16); break; } Loading @@ -109,14 +130,19 @@ bool phy_RF8256_Config_ParaFile(struct net_device* dev) rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path) eRFPath, 0x0, bMask12Bits, 0xbf); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path) eRFPath, 0x0, bMask12Bits, 0xbf); rtStatus = rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (enum rf90_radio_path)eRFPath); rtStatus = rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (enum rf90_radio_path)eRFPath); if (rtStatus != true) { RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath); RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check " "Radio[%d] Fail!!\n", eRFPath); goto phy_RF8256_Config_ParaFile_Fail; } Loading @@ -124,34 +150,61 @@ bool phy_RF8256_Config_ParaFile(struct net_device* dev) RF3_Final_Value = 0; switch (eRFPath) { case RF90_PATH_A: while (RF3_Final_Value!=RegValueToBeCheck && RetryTimes != 0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(enum rf90_radio_path)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (enum rf90_radio_path)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final " "value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); RetryTimes--; } break; case RF90_PATH_B: while (RF3_Final_Value!=RegValueToBeCheck && RetryTimes != 0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(enum rf90_radio_path)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (enum rf90_radio_path)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final " "value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); RetryTimes--; } break; case RF90_PATH_C: while (RF3_Final_Value!=RegValueToBeCheck && RetryTimes != 0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(enum rf90_radio_path)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (enum rf90_radio_path)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final " "value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); RetryTimes--; } break; case RF90_PATH_D: while (RF3_Final_Value!=RegValueToBeCheck && RetryTimes != 0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(enum rf90_radio_path)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (enum rf90_radio_path)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final " "value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); RetryTimes--; } break; Loading @@ -160,16 +213,19 @@ bool phy_RF8256_Config_ParaFile(struct net_device* dev) switch (eRFPath) { case RF90_PATH_A: case RF90_PATH_C: rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); break; case RF90_PATH_B: case RF90_PATH_D: rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); break; } if (ret) { RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!", eRFPath); RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():" "Radio[%d] Fail!!", eRFPath); goto phy_RF8256_Config_ParaFile_Fail; } Loading @@ -189,8 +245,7 @@ void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel) struct r8192_priv *priv = rtllib_priv(dev); TxAGC = powerlevel; if (priv->bDynamicTxLowPower == true) { if (priv->bDynamicTxLowPower == true) { if (priv->CustomerID == RT_CID_819x_Netcore) TxAGC = 0x22; else Loading @@ -211,13 +266,15 @@ void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel) u8 byte0, byte1, byte2, byte3; powerBase0 = powerlevel + priv->LegacyHTTxPowerDiff; powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) | (powerBase0 << 8) | powerBase0; powerBase1 = powerlevel; powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; powerBase1 = (powerBase1 << 24) | (powerBase1 << 16) | (powerBase1 << 8) | powerBase1; for (index=0; index<6; index++) { writeVal = (u32)(priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1)); for (index = 0; index < 6; index++) { writeVal = (u32)(priv->MCSTxPowerLevelOriginalOffset[index] + ((index < 2) ? powerBase0 : powerBase1)); byte0 = (u8)(writeVal & 0x7f); byte1 = (u8)((writeVal & 0x7f00)>>8); byte2 = (u8)((writeVal & 0x7f0000)>>16); Loading @@ -231,20 +288,17 @@ void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel) if (byte3 > 0x24) byte3 = 0x24; if (index == 3) { writeVal_tmp = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; if (index == 3) { writeVal_tmp = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0; priv->Pwr_Track = writeVal_tmp; } if (priv->bDynamicTxHighPower == true) { writeVal = 0x03030303; } else { writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; } writeVal = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0; rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); } Loading drivers/staging/rtl8192e/r8190P_rtl8256.h +6 −5 Original line number Diff line number Diff line Loading @@ -21,7 +21,8 @@ #define RTL8225H #define RTL819X_TOTAL_RF_PATH 2 extern void PHY_SetRF8256Bandwidth(struct net_device* dev , enum ht_channel_width Bandwidth); extern void PHY_SetRF8256Bandwidth(struct net_device *dev, enum ht_channel_width Bandwidth); extern bool PHY_RF8256_Config(struct net_device *dev); extern bool phy_RF8256_Config_ParaFile(struct net_device *dev); extern void PHY_SetRF8256CCKTxPower(struct net_device *dev, u8 powerlevel); Loading drivers/staging/rtl8192e/r8192E_cmdpkt.c +82 −114 Original line number Diff line number Diff line Loading @@ -30,8 +30,8 @@ \ memcpy(temp, Address, 40);\ for (i = 0; i < 40; i += 4)\ printk("\r\n %08x", temp[i]);\ }\ printk(KERN_INFO "\r\n %08x", temp[i]);\ } /*---------------------------Define functions---------------------------------*/ extern bool cmpk_message_handle_tx( Loading Loading @@ -67,7 +67,8 @@ bLastIniPkt = 1; } skb = dev_alloc_skb(frag_length + priv->rtllib->tx_headroom + 4); skb = dev_alloc_skb(frag_length + priv->rtllib->tx_headroom + 4); if (skb == NULL) { rt_status = false; Loading Loading @@ -110,7 +111,8 @@ cmpk_count_txstatistic( #ifdef ENABLE_PS enum rt_rf_power_state rtState; pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); if (rtState == eRfOff) return; Loading Loading @@ -152,10 +154,7 @@ cmpk_count_txstatistic( static void cmpk_handle_tx_feedback( struct net_device *dev, u8 * pmsg) static void cmpk_handle_tx_feedback(struct net_device *dev, u8 *pmsg) { struct r8192_priv *priv = rtllib_priv(dev); struct cmpk_txfb rx_tx_fb; /* */ Loading @@ -168,36 +167,25 @@ cmpk_handle_tx_feedback( } /* cmpk_Handle_Tx_Feedback */ void cmdpkt_beacontimerinterrupt_819xusb( struct net_device *dev ) void cmdpkt_beacontimerinterrupt_819xusb(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); u16 tx_rate; { if ((priv->rtllib->current_network.mode == IEEE_A) || (priv->rtllib->current_network.mode == IEEE_N_5G) || ((priv->rtllib->current_network.mode == IEEE_N_24G) && (!priv->rtllib->pHTInfo->bCurSuppCCK))) { ((priv->rtllib->current_network.mode == IEEE_N_24G) && (!priv->rtllib->pHTInfo->bCurSuppCCK))) { tx_rate = 60; DMESG("send beacon frame tx rate is 6Mbpm\n"); } else { } else { tx_rate = 10; DMESG("send beacon frame tx rate is 1Mbpm\n"); } } } static void cmpk_handle_interrupt_status( struct net_device *dev, u8* pmsg) static void cmpk_handle_interrupt_status(struct net_device *dev, u8 *pmsg) { struct cmpk_intr_sta rx_intr_status; /* */ struct r8192_priv *priv = rtllib_priv(dev); Loading @@ -206,48 +194,36 @@ cmpk_handle_interrupt_status( rx_intr_status.length = pmsg[1]; if (rx_intr_status.length != (sizeof(struct cmpk_intr_sta) - 2)) { if (rx_intr_status.length != (sizeof(struct cmpk_intr_sta) - 2)) { DMESG("cmpk_Handle_Interrupt_Status: wrong length!\n"); return; } if ( priv->rtllib->iw_mode == IW_MODE_ADHOC) { if (priv->rtllib->iw_mode == IW_MODE_ADHOC) { rx_intr_status.interrupt_status = *((u32 *)(pmsg + 4)); DMESG("interrupt status = 0x%x\n", rx_intr_status.interrupt_status); DMESG("interrupt status = 0x%x\n", rx_intr_status.interrupt_status); if (rx_intr_status.interrupt_status & ISR_TxBcnOk) { if (rx_intr_status.interrupt_status & ISR_TxBcnOk) { priv->rtllib->bibsscoordinator = true; priv->stats.txbeaconokint++; } else if (rx_intr_status.interrupt_status & ISR_TxBcnErr) { } else if (rx_intr_status.interrupt_status & ISR_TxBcnErr) { priv->rtllib->bibsscoordinator = false; priv->stats.txbeaconerr++; } if (rx_intr_status.interrupt_status & ISR_BcnTimerIntr) { cmdpkt_beacontimerinterrupt_819xusb(dev); } } DMESG("<---- cmpk_handle_interrupt_status()\n"); } /* cmpk_handle_interrupt_status */ static void cmpk_handle_query_config_rx( struct net_device *dev, u8* pmsg) static void cmpk_handle_query_config_rx(struct net_device *dev, u8 *pmsg) { cmpk_query_cfg_t rx_query_cfg; /* */ Loading @@ -274,12 +250,11 @@ static void cmpk_count_tx_status( struct net_device *dev, enum rt_rf_power_state rtstate; pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); if (rtState == eRfOff) { return; } #endif priv->stats.txfeedbackok += pstx_status->txok; Loading Loading @@ -309,23 +284,15 @@ static void cmpk_count_tx_status( struct net_device *dev, static void cmpk_handle_tx_status( struct net_device *dev, u8* pmsg) static void cmpk_handle_tx_status(struct net_device *dev, u8 *pmsg) { struct cmpk_tx_status rx_tx_sts; /* */ memcpy((void *)&rx_tx_sts, (void *)pmsg, sizeof(struct cmpk_tx_status)); cmpk_count_tx_status(dev, &rx_tx_sts); } static void cmpk_handle_tx_rate_history( struct net_device *dev, u8* pmsg) static void cmpk_handle_tx_rate_history(struct net_device *dev, u8 *pmsg) { struct cmpk_tx_rahis *ptxrate; u8 i, j; Loading @@ -335,18 +302,16 @@ cmpk_handle_tx_rate_history( #ifdef ENABLE_PS pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); if (rtState == eRfOff) { return; } #endif ptemp = (u32 *)pmsg; for (i = 0; i < (length/4); i++) { for (i = 0; i < (length / 4); i++) { u16 temp1, temp2; temp1 = ptemp[i] & 0x0000FFFF; Loading @@ -357,12 +322,9 @@ cmpk_handle_tx_rate_history( ptxrate = (struct cmpk_tx_rahis *)pmsg; if (ptxrate == NULL) { return; } for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) { if (i < 4) priv->stats.txrate.cck[i] += ptxrate->cck[i]; Loading @@ -370,7 +332,8 @@ cmpk_handle_tx_rate_history( priv->stats.txrate.ofdm[i] += ptxrate->ofdm[i]; for (j = 0; j < 4; j++) priv->stats.txrate.ht_mcs[j][i] += ptxrate->ht_mcs[j][i]; priv->stats.txrate.ht_mcs[j][i] += ptxrate->ht_mcs[j][i]; } } Loading @@ -389,8 +352,7 @@ cmpk_message_handle_rx( RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx()\n"); if (/*(prfd->queue_id != CMPK_RX_QUEUE_ID) || */(pstats== NULL)) { if (pstats == NULL) { /* Print error message. */ /*RT_TRACE(COMP_SEND, DebugLevel, ("\n\r[CMPK]-->Err queue id or pointer"));*/ Loading @@ -403,43 +365,49 @@ cmpk_message_handle_rx( element_id = pcmd_buff[0]; while (total_length > 0 || exe_cnt++ >100) { while (total_length > 0 || exe_cnt++ > 100) { element_id = pcmd_buff[0]; switch (element_id) { case RX_TX_FEEDBACK: RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():RX_TX_FEEDBACK\n"); RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" "RX_TX_FEEDBACK\n"); cmpk_handle_tx_feedback(dev, pcmd_buff); cmd_length = CMPK_RX_TX_FB_SIZE; break; case RX_INTERRUPT_STATUS: RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():RX_INTERRUPT_STATUS\n"); RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" "RX_INTERRUPT_STATUS\n"); cmpk_handle_interrupt_status(dev, pcmd_buff); cmd_length = sizeof(struct cmpk_intr_sta); break; case BOTH_QUERY_CONFIG: RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():BOTH_QUERY_CONFIG\n"); RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" "BOTH_QUERY_CONFIG\n"); cmpk_handle_query_config_rx(dev, pcmd_buff); cmd_length = CMPK_BOTH_QUERY_CONFIG_SIZE; break; case RX_TX_STATUS: RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():RX_TX_STATUS\n"); RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" "RX_TX_STATUS\n"); cmpk_handle_tx_status(dev, pcmd_buff); cmd_length = CMPK_RX_TX_STS_SIZE; break; case RX_TX_PER_PKT_FEEDBACK: RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():RX_TX_PER_PKT_FEEDBACK\n"); RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" "RX_TX_PER_PKT_FEEDBACK\n"); cmd_length = CMPK_RX_TX_FB_SIZE; break; case RX_TX_RATE_HISTORY: RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():RX_TX_HISTORY\n"); RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" "RX_TX_HISTORY\n"); cmpk_handle_tx_rate_history(dev, pcmd_buff); cmd_length = CMPK_TX_RAHIS_SIZE; break; default: RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():unknow CMD Element\n"); RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" "unknow CMD Element\n"); return 1; } Loading drivers/staging/rtl8192e/r8192E_cmdpkt.h +24 −21 Original line number Diff line number Diff line Loading @@ -149,8 +149,11 @@ enum cmpk_element { RX_CMD_ELE_MAX }; extern u32 cmpk_message_handle_rx(struct net_device *dev, struct rtllib_rx_stats * pstats); extern bool cmpk_message_handle_tx(struct net_device *dev, u8* codevirtualaddress, u32 packettype, u32 buffer_len); extern u32 cmpk_message_handle_rx(struct net_device *dev, struct rtllib_rx_stats *pstats); extern bool cmpk_message_handle_tx(struct net_device *dev, u8 *codevirtualaddress, u32 packettype, u32 buffer_len); #endif Loading
drivers/staging/rtl8192e/r8190P_def.h +36 −36 Original line number Diff line number Diff line Loading @@ -85,7 +85,7 @@ enum rtl819x_loopback { #define BT_QA_BOARD 1 #define BT_FPGA 2 #define Rx_Smooth_Factor 20 #define RX_SMOOTH 20 #define QSLT_BK 0x1 #define QSLT_BE 0x0 Loading
drivers/staging/rtl8192e/r8190P_rtl8256.c +120 −66 Original line number Diff line number Diff line Loading @@ -22,7 +22,8 @@ #include "r8192E_phy.h" #include "r8190P_rtl8256.h" void PHY_SetRF8256Bandwidth(struct net_device* dev , enum ht_channel_width Bandwidth) void PHY_SetRF8256Bandwidth(struct net_device *dev, enum ht_channel_width Bandwidth) { u8 eRFPath; struct r8192_priv *priv = rtllib_priv(dev); Loading @@ -33,30 +34,47 @@ void PHY_SetRF8256Bandwidth(struct net_device* dev , enum ht_channel_width Bandw switch (Bandwidth) { case HT_CHANNEL_WIDTH_20: if (priv->card_8192_version == VERSION_8190_BD || priv->card_8192_version == VERSION_8190_BE) { rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0b, bMask12Bits, 0x100); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x2c, bMask12Bits, 0x3d7); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0e, bMask12Bits, 0x021); if (priv->card_8192_version == VERSION_8190_BD || priv->card_8192_version == VERSION_8190_BE) { rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0b, bMask12Bits, 0x100); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x2c, bMask12Bits, 0x3d7); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0e, bMask12Bits, 0x021); } else { RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n"); RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): " "unknown hardware version\n"); } break; case HT_CHANNEL_WIDTH_20_40: if (priv->card_8192_version == VERSION_8190_BD ||priv->card_8192_version == VERSION_8190_BE) { rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0b, bMask12Bits, 0x300); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x2c, bMask12Bits, 0x3ff); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0e, bMask12Bits, 0x0e1); if (priv->card_8192_version == VERSION_8190_BD || priv->card_8192_version == VERSION_8190_BE) { rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0b, bMask12Bits, 0x300); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x2c, bMask12Bits, 0x3ff); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0e, bMask12Bits, 0x0e1); } else { RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n"); RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): " "unknown hardware version\n"); } break; default: RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ); RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown " "Bandwidth: %#X\n", Bandwidth); break; } Loading Loading @@ -87,7 +105,8 @@ bool phy_RF8256_Config_ParaFile(struct net_device* dev) u8 ConstRetryTimes = 5, RetryTimes = 5; u8 ret = 0; for (eRFPath = (enum rf90_radio_path)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++) { for (eRFPath = (enum rf90_radio_path)RF90_PATH_A; eRFPath < priv->NumTotalRFPath; eRFPath++) { if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) continue; Loading @@ -97,11 +116,13 @@ bool phy_RF8256_Config_ParaFile(struct net_device* dev) switch (eRFPath) { case RF90_PATH_A: case RF90_PATH_C: u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV); u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV); break; case RF90_PATH_B: case RF90_PATH_D: u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16); u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16); break; } Loading @@ -109,14 +130,19 @@ bool phy_RF8256_Config_ParaFile(struct net_device* dev) rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path) eRFPath, 0x0, bMask12Bits, 0xbf); rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path) eRFPath, 0x0, bMask12Bits, 0xbf); rtStatus = rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (enum rf90_radio_path)eRFPath); rtStatus = rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (enum rf90_radio_path)eRFPath); if (rtStatus != true) { RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath); RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check " "Radio[%d] Fail!!\n", eRFPath); goto phy_RF8256_Config_ParaFile_Fail; } Loading @@ -124,34 +150,61 @@ bool phy_RF8256_Config_ParaFile(struct net_device* dev) RF3_Final_Value = 0; switch (eRFPath) { case RF90_PATH_A: while (RF3_Final_Value!=RegValueToBeCheck && RetryTimes != 0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(enum rf90_radio_path)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (enum rf90_radio_path)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final " "value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); RetryTimes--; } break; case RF90_PATH_B: while (RF3_Final_Value!=RegValueToBeCheck && RetryTimes != 0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(enum rf90_radio_path)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (enum rf90_radio_path)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final " "value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); RetryTimes--; } break; case RF90_PATH_C: while (RF3_Final_Value!=RegValueToBeCheck && RetryTimes != 0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(enum rf90_radio_path)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (enum rf90_radio_path)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final " "value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); RetryTimes--; } break; case RF90_PATH_D: while (RF3_Final_Value!=RegValueToBeCheck && RetryTimes != 0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(enum rf90_radio_path)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) { ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (enum rf90_radio_path)eRFPath); RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits); RT_TRACE(COMP_RF, "RF %d %d register final " "value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); RetryTimes--; } break; Loading @@ -160,16 +213,19 @@ bool phy_RF8256_Config_ParaFile(struct net_device* dev) switch (eRFPath) { case RF90_PATH_A: case RF90_PATH_C: rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); break; case RF90_PATH_B: case RF90_PATH_D: rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); break; } if (ret) { RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!", eRFPath); RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():" "Radio[%d] Fail!!", eRFPath); goto phy_RF8256_Config_ParaFile_Fail; } Loading @@ -189,8 +245,7 @@ void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel) struct r8192_priv *priv = rtllib_priv(dev); TxAGC = powerlevel; if (priv->bDynamicTxLowPower == true) { if (priv->bDynamicTxLowPower == true) { if (priv->CustomerID == RT_CID_819x_Netcore) TxAGC = 0x22; else Loading @@ -211,13 +266,15 @@ void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel) u8 byte0, byte1, byte2, byte3; powerBase0 = powerlevel + priv->LegacyHTTxPowerDiff; powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) | (powerBase0 << 8) | powerBase0; powerBase1 = powerlevel; powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; powerBase1 = (powerBase1 << 24) | (powerBase1 << 16) | (powerBase1 << 8) | powerBase1; for (index=0; index<6; index++) { writeVal = (u32)(priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1)); for (index = 0; index < 6; index++) { writeVal = (u32)(priv->MCSTxPowerLevelOriginalOffset[index] + ((index < 2) ? powerBase0 : powerBase1)); byte0 = (u8)(writeVal & 0x7f); byte1 = (u8)((writeVal & 0x7f00)>>8); byte2 = (u8)((writeVal & 0x7f0000)>>16); Loading @@ -231,20 +288,17 @@ void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel) if (byte3 > 0x24) byte3 = 0x24; if (index == 3) { writeVal_tmp = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; if (index == 3) { writeVal_tmp = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0; priv->Pwr_Track = writeVal_tmp; } if (priv->bDynamicTxHighPower == true) { writeVal = 0x03030303; } else { writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0; } writeVal = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0; rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); } Loading
drivers/staging/rtl8192e/r8190P_rtl8256.h +6 −5 Original line number Diff line number Diff line Loading @@ -21,7 +21,8 @@ #define RTL8225H #define RTL819X_TOTAL_RF_PATH 2 extern void PHY_SetRF8256Bandwidth(struct net_device* dev , enum ht_channel_width Bandwidth); extern void PHY_SetRF8256Bandwidth(struct net_device *dev, enum ht_channel_width Bandwidth); extern bool PHY_RF8256_Config(struct net_device *dev); extern bool phy_RF8256_Config_ParaFile(struct net_device *dev); extern void PHY_SetRF8256CCKTxPower(struct net_device *dev, u8 powerlevel); Loading
drivers/staging/rtl8192e/r8192E_cmdpkt.c +82 −114 Original line number Diff line number Diff line Loading @@ -30,8 +30,8 @@ \ memcpy(temp, Address, 40);\ for (i = 0; i < 40; i += 4)\ printk("\r\n %08x", temp[i]);\ }\ printk(KERN_INFO "\r\n %08x", temp[i]);\ } /*---------------------------Define functions---------------------------------*/ extern bool cmpk_message_handle_tx( Loading Loading @@ -67,7 +67,8 @@ bLastIniPkt = 1; } skb = dev_alloc_skb(frag_length + priv->rtllib->tx_headroom + 4); skb = dev_alloc_skb(frag_length + priv->rtllib->tx_headroom + 4); if (skb == NULL) { rt_status = false; Loading Loading @@ -110,7 +111,8 @@ cmpk_count_txstatistic( #ifdef ENABLE_PS enum rt_rf_power_state rtState; pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); if (rtState == eRfOff) return; Loading Loading @@ -152,10 +154,7 @@ cmpk_count_txstatistic( static void cmpk_handle_tx_feedback( struct net_device *dev, u8 * pmsg) static void cmpk_handle_tx_feedback(struct net_device *dev, u8 *pmsg) { struct r8192_priv *priv = rtllib_priv(dev); struct cmpk_txfb rx_tx_fb; /* */ Loading @@ -168,36 +167,25 @@ cmpk_handle_tx_feedback( } /* cmpk_Handle_Tx_Feedback */ void cmdpkt_beacontimerinterrupt_819xusb( struct net_device *dev ) void cmdpkt_beacontimerinterrupt_819xusb(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); u16 tx_rate; { if ((priv->rtllib->current_network.mode == IEEE_A) || (priv->rtllib->current_network.mode == IEEE_N_5G) || ((priv->rtllib->current_network.mode == IEEE_N_24G) && (!priv->rtllib->pHTInfo->bCurSuppCCK))) { ((priv->rtllib->current_network.mode == IEEE_N_24G) && (!priv->rtllib->pHTInfo->bCurSuppCCK))) { tx_rate = 60; DMESG("send beacon frame tx rate is 6Mbpm\n"); } else { } else { tx_rate = 10; DMESG("send beacon frame tx rate is 1Mbpm\n"); } } } static void cmpk_handle_interrupt_status( struct net_device *dev, u8* pmsg) static void cmpk_handle_interrupt_status(struct net_device *dev, u8 *pmsg) { struct cmpk_intr_sta rx_intr_status; /* */ struct r8192_priv *priv = rtllib_priv(dev); Loading @@ -206,48 +194,36 @@ cmpk_handle_interrupt_status( rx_intr_status.length = pmsg[1]; if (rx_intr_status.length != (sizeof(struct cmpk_intr_sta) - 2)) { if (rx_intr_status.length != (sizeof(struct cmpk_intr_sta) - 2)) { DMESG("cmpk_Handle_Interrupt_Status: wrong length!\n"); return; } if ( priv->rtllib->iw_mode == IW_MODE_ADHOC) { if (priv->rtllib->iw_mode == IW_MODE_ADHOC) { rx_intr_status.interrupt_status = *((u32 *)(pmsg + 4)); DMESG("interrupt status = 0x%x\n", rx_intr_status.interrupt_status); DMESG("interrupt status = 0x%x\n", rx_intr_status.interrupt_status); if (rx_intr_status.interrupt_status & ISR_TxBcnOk) { if (rx_intr_status.interrupt_status & ISR_TxBcnOk) { priv->rtllib->bibsscoordinator = true; priv->stats.txbeaconokint++; } else if (rx_intr_status.interrupt_status & ISR_TxBcnErr) { } else if (rx_intr_status.interrupt_status & ISR_TxBcnErr) { priv->rtllib->bibsscoordinator = false; priv->stats.txbeaconerr++; } if (rx_intr_status.interrupt_status & ISR_BcnTimerIntr) { cmdpkt_beacontimerinterrupt_819xusb(dev); } } DMESG("<---- cmpk_handle_interrupt_status()\n"); } /* cmpk_handle_interrupt_status */ static void cmpk_handle_query_config_rx( struct net_device *dev, u8* pmsg) static void cmpk_handle_query_config_rx(struct net_device *dev, u8 *pmsg) { cmpk_query_cfg_t rx_query_cfg; /* */ Loading @@ -274,12 +250,11 @@ static void cmpk_count_tx_status( struct net_device *dev, enum rt_rf_power_state rtstate; pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); if (rtState == eRfOff) { return; } #endif priv->stats.txfeedbackok += pstx_status->txok; Loading Loading @@ -309,23 +284,15 @@ static void cmpk_count_tx_status( struct net_device *dev, static void cmpk_handle_tx_status( struct net_device *dev, u8* pmsg) static void cmpk_handle_tx_status(struct net_device *dev, u8 *pmsg) { struct cmpk_tx_status rx_tx_sts; /* */ memcpy((void *)&rx_tx_sts, (void *)pmsg, sizeof(struct cmpk_tx_status)); cmpk_count_tx_status(dev, &rx_tx_sts); } static void cmpk_handle_tx_rate_history( struct net_device *dev, u8* pmsg) static void cmpk_handle_tx_rate_history(struct net_device *dev, u8 *pmsg) { struct cmpk_tx_rahis *ptxrate; u8 i, j; Loading @@ -335,18 +302,16 @@ cmpk_handle_tx_rate_history( #ifdef ENABLE_PS pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); if (rtState == eRfOff) { return; } #endif ptemp = (u32 *)pmsg; for (i = 0; i < (length/4); i++) { for (i = 0; i < (length / 4); i++) { u16 temp1, temp2; temp1 = ptemp[i] & 0x0000FFFF; Loading @@ -357,12 +322,9 @@ cmpk_handle_tx_rate_history( ptxrate = (struct cmpk_tx_rahis *)pmsg; if (ptxrate == NULL) { return; } for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) { if (i < 4) priv->stats.txrate.cck[i] += ptxrate->cck[i]; Loading @@ -370,7 +332,8 @@ cmpk_handle_tx_rate_history( priv->stats.txrate.ofdm[i] += ptxrate->ofdm[i]; for (j = 0; j < 4; j++) priv->stats.txrate.ht_mcs[j][i] += ptxrate->ht_mcs[j][i]; priv->stats.txrate.ht_mcs[j][i] += ptxrate->ht_mcs[j][i]; } } Loading @@ -389,8 +352,7 @@ cmpk_message_handle_rx( RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx()\n"); if (/*(prfd->queue_id != CMPK_RX_QUEUE_ID) || */(pstats== NULL)) { if (pstats == NULL) { /* Print error message. */ /*RT_TRACE(COMP_SEND, DebugLevel, ("\n\r[CMPK]-->Err queue id or pointer"));*/ Loading @@ -403,43 +365,49 @@ cmpk_message_handle_rx( element_id = pcmd_buff[0]; while (total_length > 0 || exe_cnt++ >100) { while (total_length > 0 || exe_cnt++ > 100) { element_id = pcmd_buff[0]; switch (element_id) { case RX_TX_FEEDBACK: RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():RX_TX_FEEDBACK\n"); RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" "RX_TX_FEEDBACK\n"); cmpk_handle_tx_feedback(dev, pcmd_buff); cmd_length = CMPK_RX_TX_FB_SIZE; break; case RX_INTERRUPT_STATUS: RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():RX_INTERRUPT_STATUS\n"); RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" "RX_INTERRUPT_STATUS\n"); cmpk_handle_interrupt_status(dev, pcmd_buff); cmd_length = sizeof(struct cmpk_intr_sta); break; case BOTH_QUERY_CONFIG: RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():BOTH_QUERY_CONFIG\n"); RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" "BOTH_QUERY_CONFIG\n"); cmpk_handle_query_config_rx(dev, pcmd_buff); cmd_length = CMPK_BOTH_QUERY_CONFIG_SIZE; break; case RX_TX_STATUS: RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():RX_TX_STATUS\n"); RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" "RX_TX_STATUS\n"); cmpk_handle_tx_status(dev, pcmd_buff); cmd_length = CMPK_RX_TX_STS_SIZE; break; case RX_TX_PER_PKT_FEEDBACK: RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():RX_TX_PER_PKT_FEEDBACK\n"); RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" "RX_TX_PER_PKT_FEEDBACK\n"); cmd_length = CMPK_RX_TX_FB_SIZE; break; case RX_TX_RATE_HISTORY: RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():RX_TX_HISTORY\n"); RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" "RX_TX_HISTORY\n"); cmpk_handle_tx_rate_history(dev, pcmd_buff); cmd_length = CMPK_TX_RAHIS_SIZE; break; default: RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():unknow CMD Element\n"); RT_TRACE(COMP_CMDPKT, "---->cmpk_message_handle_rx():" "unknow CMD Element\n"); return 1; } Loading
drivers/staging/rtl8192e/r8192E_cmdpkt.h +24 −21 Original line number Diff line number Diff line Loading @@ -149,8 +149,11 @@ enum cmpk_element { RX_CMD_ELE_MAX }; extern u32 cmpk_message_handle_rx(struct net_device *dev, struct rtllib_rx_stats * pstats); extern bool cmpk_message_handle_tx(struct net_device *dev, u8* codevirtualaddress, u32 packettype, u32 buffer_len); extern u32 cmpk_message_handle_rx(struct net_device *dev, struct rtllib_rx_stats *pstats); extern bool cmpk_message_handle_tx(struct net_device *dev, u8 *codevirtualaddress, u32 packettype, u32 buffer_len); #endif