Commit 189f73e3 authored by Tony Cheng's avatar Tony Cheng Committed by Alex Deucher
Browse files

drm/amd/display: change order of HUBP and MPC disable according to HW guide 



blank hubp first before disconnect MPC

Signed-off-by: default avatarTony Cheng <tony.cheng@amd.com>
Reviewed-by: default avatarEric Yang <eric.yang2@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ef347b3b

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+7 −3
Original line number Diff line number Diff line
@@ -477,9 +477,14 @@ static void reset_front_end( 
	if (mpcc->opp_id == 0xf)

		return;



	mi->funcs->dcc_control(mi, false, false);

	tg->funcs->lock(tg);



	mi->funcs->dcc_control(mi, false, false);

	mi->funcs->set_blank(mi, true);

	REG_WAIT(DCHUBP_CNTL[fe_idx],

			HUBP_NO_OUTSTANDING_REQ, 1,

			1, 200);



	mpcc_cfg.opp_id = 0xf;

	mpcc_cfg.top_dpp_id = 0xf;

	mpcc_cfg.bot_mpcc_id = 0xf;
@@ -491,8 +496,7 @@ static void reset_front_end( 
	REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, 20000, 200000);



	mpcc->funcs->wait_for_idle(mpcc);

	mi->funcs->set_blank(mi, true);

	REG_WAIT(DCHUBP_CNTL[fe_idx], HUBP_NO_OUTSTANDING_REQ, 1, 20000, 200000);



	REG_UPDATE(HUBP_CLK_CNTL[fe_idx], HUBP_CLOCK_ENABLE, 0);

	REG_UPDATE(DPP_CONTROL[fe_idx], DPP_CLOCK_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c

+3 −1
Original line number Diff line number Diff line
@@ -117,7 +117,9 @@ static void dcn10_mpcc_wait_idle(struct mpcc *mpcc) 
{

	struct dcn10_mpcc *mpcc10 = TO_DCN10_MPCC(mpcc);



	REG_WAIT(MPCC_STATUS, MPCC_BUSY, 0, 1000, 1000);

	REG_WAIT(MPCC_STATUS,

			MPCC_BUSY, 0,

			1000, 1000);

}