Commit 18ef7544 authored by Ran Sun's avatar Ran Sun Committed by Alex Deucher
Browse files

drm/amdgpu: Clean up errors in dce_v8_0.c 



Fix the following errors reported by checkpatch:

ERROR: that open brace { should be on the previous line
ERROR: code indent should use tabs where possible
ERROR: space required before the open brace '{'

Signed-off-by: default avatarRan Sun <sunran001@208suo.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 665ba81b

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

+14 −23
Original line number Diff line number Diff line
@@ -53,8 +53,7 @@ 
static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);

static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);



static const u32 crtc_offsets[6] =

{

static const u32 crtc_offsets[6] = {

	CRTC0_REGISTER_OFFSET,

	CRTC1_REGISTER_OFFSET,

	CRTC2_REGISTER_OFFSET,
@@ -63,8 +62,7 @@ static const u32 crtc_offsets[6] = 
	CRTC5_REGISTER_OFFSET

};



static const u32 hpd_offsets[] =

{

static const u32 hpd_offsets[] = {

	HPD0_REGISTER_OFFSET,

	HPD1_REGISTER_OFFSET,

	HPD2_REGISTER_OFFSET,
@@ -1379,8 +1377,7 @@ static void dce_v8_0_audio_enable(struct amdgpu_device *adev, 
		enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);

}



static const u32 pin_offsets[7] =

{

static const u32 pin_offsets[7] = {

	(0x1780 - 0x1780),

	(0x1786 - 0x1780),

	(0x178c - 0x1780),
@@ -1740,8 +1737,7 @@ static void dce_v8_0_afmt_fini(struct amdgpu_device *adev) 
	}

}



static const u32 vga_control_regs[6] =

{

static const u32 vga_control_regs[6] = {

	mmD1VGA_CONTROL,

	mmD2VGA_CONTROL,

	mmD3VGA_CONTROL,
@@ -3544,8 +3540,7 @@ static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev) 
	adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;

}



const struct amdgpu_ip_block_version dce_v8_0_ip_block =

{

const struct amdgpu_ip_block_version dce_v8_0_ip_block = {

	.type = AMD_IP_BLOCK_TYPE_DCE,

	.major = 8,

	.minor = 0,
@@ -3553,8 +3548,7 @@ const struct amdgpu_ip_block_version dce_v8_0_ip_block = 
	.funcs = &dce_v8_0_ip_funcs,

};



const struct amdgpu_ip_block_version dce_v8_1_ip_block =

{

const struct amdgpu_ip_block_version dce_v8_1_ip_block = {

	.type = AMD_IP_BLOCK_TYPE_DCE,

	.major = 8,

	.minor = 1,
@@ -3562,8 +3556,7 @@ const struct amdgpu_ip_block_version dce_v8_1_ip_block = 
	.funcs = &dce_v8_0_ip_funcs,

};



const struct amdgpu_ip_block_version dce_v8_2_ip_block =

{

const struct amdgpu_ip_block_version dce_v8_2_ip_block = {

	.type = AMD_IP_BLOCK_TYPE_DCE,

	.major = 8,

	.minor = 2,
@@ -3571,8 +3564,7 @@ const struct amdgpu_ip_block_version dce_v8_2_ip_block = 
	.funcs = &dce_v8_0_ip_funcs,

};



const struct amdgpu_ip_block_version dce_v8_3_ip_block =

{

const struct amdgpu_ip_block_version dce_v8_3_ip_block = {

	.type = AMD_IP_BLOCK_TYPE_DCE,

	.major = 8,

	.minor = 3,
@@ -3580,8 +3572,7 @@ const struct amdgpu_ip_block_version dce_v8_3_ip_block = 
	.funcs = &dce_v8_0_ip_funcs,

};



const struct amdgpu_ip_block_version dce_v8_5_ip_block =

{

const struct amdgpu_ip_block_version dce_v8_5_ip_block = {

	.type = AMD_IP_BLOCK_TYPE_DCE,

	.major = 8,

	.minor = 5,