Commit 1ab4ef06 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events: Add Intel meteorlake 

Events are v1.00, there are no metrics yet.

Use script at:
https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py



to download and generate the events and metrics. Manually copy
the meteorlake files into perf and update mapfile.csv.

Tested on a non-meteorlake with 'perf test':
 10: PMU events                                                      :
 10.1: PMU event table sanity                                        : Ok
 10.2: PMU event map aliases                                         : Ok
 10.3: Parsing of PMU event table metrics                            : Ok
 10.4: Parsing of PMU event table metrics with fake PMUs             : Ok

Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Kshipra Bopardikar <kshipra.bopardikar@intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sedat Dilek <sedat.dilek@gmail.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: http://lore.kernel.org/lkml/20220727220832.2865794-19-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent ae7bcd60

tools/perf/pmu-events/arch/x86/mapfile.csv

+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ GenuineIntel-6-3A,v22,ivybridge,core 
GenuineIntel-6-3E,v21,ivytown,core

GenuineIntel-6-2D,v21,jaketown,core

GenuineIntel-6-(57|85),v9,knightslanding,core

GenuineIntel-6-AA,v1.00,meteorlake,core

GenuineIntel-6-1E,v2,nehalemep,core

GenuineIntel-6-1F,v2,nehalemep,core

GenuineIntel-6-1A,v2,nehalemep,core

tools/perf/pmu-events/arch/x86/meteorlake/cache.json

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+262 −0
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x2e",

        "EventName": "LONGEST_LAT_CACHE.MISS",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "200003",

        "UMask": "0x41",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x2e",

        "EventName": "LONGEST_LAT_CACHE.REFERENCE",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "200003",

        "UMask": "0x4f",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of load ops retired.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",

        "PEBS": "1",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "200003",

        "UMask": "0x81",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of store ops retired.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",

        "PEBS": "1",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "200003",

        "UMask": "0x82",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "CollectPEBSRecord": "3",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x80",

        "PEBS": "2",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "TakenAlone": "1",

        "UMask": "0x5",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "CollectPEBSRecord": "3",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x10",

        "PEBS": "2",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "TakenAlone": "1",

        "UMask": "0x5",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "CollectPEBSRecord": "3",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x100",

        "PEBS": "2",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "TakenAlone": "1",

        "UMask": "0x5",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "CollectPEBSRecord": "3",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x20",

        "PEBS": "2",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "TakenAlone": "1",

        "UMask": "0x5",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "CollectPEBSRecord": "3",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x4",

        "PEBS": "2",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "TakenAlone": "1",

        "UMask": "0x5",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "CollectPEBSRecord": "3",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x200",

        "PEBS": "2",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "TakenAlone": "1",

        "UMask": "0x5",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "CollectPEBSRecord": "3",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x40",

        "PEBS": "2",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "TakenAlone": "1",

        "UMask": "0x5",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",

        "CollectPEBSRecord": "3",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x8",

        "PEBS": "2",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "TakenAlone": "1",

        "UMask": "0x5",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of  stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",

        "CollectPEBSRecord": "3",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",

        "PEBS": "2",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "UMask": "0x6",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "L2 code requests",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x24",

        "EventName": "L2_RQSTS.ALL_CODE_RD",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0xe4",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Demand Data Read access L2 cache",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x24",

        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "UMask": "0xe1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x2e",

        "EventName": "LONGEST_LAT_CACHE.MISS",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "100003",

        "UMask": "0x41",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x2e",

        "EventName": "LONGEST_LAT_CACHE.REFERENCE",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "100003",

        "UMask": "0x4f",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Retired load instructions.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_INST_RETIRED.ALL_LOADS",

        "PEBS": "1",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "UMask": "0x81",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Retired store instructions.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_INST_RETIRED.ALL_STORES",

        "L1_Hit_Indication": "1",

        "PEBS": "1",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "UMask": "0x82",

        "Unit": "cpu_core"

    }

]

tools/perf/pmu-events/arch/x86/meteorlake/frontend.json

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+24 −0
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x80",

        "EventName": "ICACHE.ACCESSES",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "200003",

        "UMask": "0x3",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x80",

        "EventName": "ICACHE.MISSES",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "200003",

        "UMask": "0x2",

        "Unit": "cpu_atom"

    }

]

tools/perf/pmu-events/arch/x86/meteorlake/memory.json

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[

    {

        "BriefDescription": "Counts cacheable demand data reads were not supplied by the L3 cache.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00001",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO were not supplied by the L3 cache.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_RFO.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00002",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x80",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "1009",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x10",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "20011",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x100",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "503",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x20",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "100007",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x4",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "100003",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x200",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "101",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x40",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "2003",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",

        "CollectPEBSRecord": "2",

        "Counter": "1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x8",

        "PEBS": "2",

        "PEBScounters": "1,2,3,4,5,6,7",

        "SampleAfterValue": "50021",

        "TakenAlone": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",

        "CollectPEBSRecord": "2",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",

        "PEBS": "2",

        "SampleAfterValue": "1000003",

        "UMask": "0x2",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00001",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_RFO.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3FBFC00002",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    }

]

tools/perf/pmu-events/arch/x86/meteorlake/other.json

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Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts cacheable demand data reads Catch all value for any response types - this includes response types not define in the OCR.  If this is set all other response types will be ignored",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10001",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO Catch all value for any response types - this includes response types not define in the OCR.  If this is set all other response types will be ignored",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10002",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts demand data reads that have any type of response.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10001",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10002",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    }

]