Commit 1aba2af5 authored by Jesse Taube's avatar Jesse Taube Committed by Jernej Skrabec
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ARM: dts: suniv: F1C100: add clock and reset macros 



Include clock and reset macros and replace magic numbers.

Signed-off-by: default avatarJesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: default avatarAndre Przywara <andre.przywara@arm.com>
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Acked-by: default avatarSamuel Holland <samuel@sholland.org>
Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220317162349.739636-6-andre.przywara@arm.com
parent fb2dcdd7

arch/arm/boot/dts/suniv-f1c100s.dtsi

+10 −7
Original line number Diff line number Diff line
@@ -4,6 +4,9 @@ 
 * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>

 */



#include <dt-bindings/clock/suniv-ccu-f1c100s.h>

#include <dt-bindings/reset/suniv-ccu-f1c100s.h>



/ {

	#address-cells = <1>;

	#size-cells = <1>;
@@ -82,7 +85,7 @@ pio: pinctrl@1c20800 { 
			compatible = "allwinner,suniv-f1c100s-pinctrl";

			reg = <0x01c20800 0x400>;

			interrupts = <38>, <39>, <40>;

			clocks = <&ccu 37>, <&osc24M>, <&osc32k>;

			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;

			clock-names = "apb", "hosc", "losc";

			gpio-controller;

			interrupt-controller;
@@ -116,8 +119,8 @@ uart0: serial@1c25000 { 
			interrupts = <1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&ccu 38>;

			resets = <&ccu 24>;

			clocks = <&ccu CLK_BUS_UART0>;

			resets = <&ccu RST_BUS_UART0>;

			status = "disabled";

		};
@@ -127,8 +130,8 @@ uart1: serial@1c25400 { 
			interrupts = <2>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&ccu 39>;

			resets = <&ccu 25>;

			clocks = <&ccu CLK_BUS_UART1>;

			resets = <&ccu RST_BUS_UART1>;

			status = "disabled";

		};
@@ -138,8 +141,8 @@ uart2: serial@1c25800 { 
			interrupts = <3>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&ccu 40>;

			resets = <&ccu 26>;

			clocks = <&ccu CLK_BUS_UART2>;

			resets = <&ccu RST_BUS_UART2>;

			status = "disabled";

		};

	};