Loading arch/arm/mach-omap2/clock.c +2 −11 Original line number Diff line number Diff line Loading @@ -1160,8 +1160,8 @@ int __init omap2_clk_init(void) clk_enable(&sync_32k_ick); clk_enable(&omapctrl_ick); /* Force the APLLs active during bootup to avoid disabling and * enabling them unnecessarily. */ /* Force the APLLs always active. The clocks are idled * automatically by hardware. */ clk_enable(&apll96_ck); clk_enable(&apll54_ck); Loading @@ -1174,12 +1174,3 @@ int __init omap2_clk_init(void) return 0; } static int __init omap2_disable_aplls(void) { clk_disable(&apll96_ck); clk_disable(&apll54_ck); return 0; } late_initcall(omap2_disable_aplls); Loading
arch/arm/mach-omap2/clock.c +2 −11 Original line number Diff line number Diff line Loading @@ -1160,8 +1160,8 @@ int __init omap2_clk_init(void) clk_enable(&sync_32k_ick); clk_enable(&omapctrl_ick); /* Force the APLLs active during bootup to avoid disabling and * enabling them unnecessarily. */ /* Force the APLLs always active. The clocks are idled * automatically by hardware. */ clk_enable(&apll96_ck); clk_enable(&apll54_ck); Loading @@ -1174,12 +1174,3 @@ int __init omap2_clk_init(void) return 0; } static int __init omap2_disable_aplls(void) { clk_disable(&apll96_ck); clk_disable(&apll54_ck); return 0; } late_initcall(omap2_disable_aplls);