Commit 1abcb10d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86_platform_for_v5.19_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 platform updates from Borislav Petkov:

 - A couple of changes enabling SGI UV5 support

* tag 'x86_platform_for_v5.19_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/platform/uv: Log gap hole end size
  x86/platform/uv: Update TSC sync state for UV5
  x86/platform/uv: Update NMI Handler for UV5
parents c415b53a 327c3489

arch/x86/kernel/apic/x2apic_uv_x.c

+13 −3
Original line number Diff line number Diff line
@@ -199,7 +199,13 @@ static void __init uv_tsc_check_sync(void) 
	int mmr_shift;

	char *state;



	/* Different returns from different UV BIOS versions */

	/* UV5 guarantees synced TSCs; do not zero TSC_ADJUST */

	if (!is_uv(UV2|UV3|UV4)) {

		mark_tsc_async_resets("UV5+");

		return;

	}



	/* UV2,3,4, UV BIOS TSC sync state available */

	mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);

	mmr_shift =

		is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
@@ -1340,7 +1346,7 @@ static void __init decode_gam_params(unsigned long ptr) 
static void __init decode_gam_rng_tbl(unsigned long ptr)

{

	struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;

	unsigned long lgre = 0;

	unsigned long lgre = 0, gend = 0;

	int index = 0;

	int sock_min = 999999, pnode_min = 99999;

	int sock_max = -1, pnode_max = -1;
@@ -1374,6 +1380,9 @@ static void __init decode_gam_rng_tbl(unsigned long ptr) 
			flag, size, suffix[order],

			gre->type, gre->nasid, gre->sockid, gre->pnode);



		if (gre->type == UV_GAM_RANGE_TYPE_HOLE)

			gend = (unsigned long)gre->limit << UV_GAM_RANGE_SHFT;



		/* update to next range start */

		lgre = gre->limit;

		if (sock_min > gre->sockid)
@@ -1391,7 +1400,8 @@ static void __init decode_gam_rng_tbl(unsigned long ptr) 
	_max_pnode	= pnode_max;

	_gr_table_len	= index;



	pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode);

	pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x), pnodes(min:%x,max:%x), gap_end(%d)\n",

	  index, _min_socket, _max_socket, _min_pnode, _max_pnode, fls64(gend));

}



/* Walk through UVsystab decoding the fields */

arch/x86/platform/uv/uv_nmi.c

+11 −10
Original line number Diff line number Diff line
@@ -244,8 +244,10 @@ static inline bool uv_nmi_action_is(const char *action) 
/* Setup which NMI support is present in system */

static void uv_nmi_setup_mmrs(void)

{

	bool new_nmi_method_only = false;



	/* First determine arch specific MMRs to handshake with BIOS */

	if (UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK) {

	if (UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK) {	/* UV2,3,4 setup */

		uvh_nmi_mmrx = UVH_EVENT_OCCURRED0;

		uvh_nmi_mmrx_clear = UVH_EVENT_OCCURRED0_ALIAS;

		uvh_nmi_mmrx_shift = UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT;
@@ -255,24 +257,23 @@ static void uv_nmi_setup_mmrs(void) 
		uvh_nmi_mmrx_req = UVH_BIOS_KERNEL_MMR_ALIAS_2;

		uvh_nmi_mmrx_req_shift = 62;



	} else if (UVH_EVENT_OCCURRED1_EXTIO_INT0_MASK) {

	} else if (UVH_EVENT_OCCURRED1_EXTIO_INT0_MASK) { /* UV5+ setup */

		uvh_nmi_mmrx = UVH_EVENT_OCCURRED1;

		uvh_nmi_mmrx_clear = UVH_EVENT_OCCURRED1_ALIAS;

		uvh_nmi_mmrx_shift = UVH_EVENT_OCCURRED1_EXTIO_INT0_SHFT;

		uvh_nmi_mmrx_type = "OCRD1-EXTIO_INT0";



		uvh_nmi_mmrx_supported = UVH_EXTIO_INT0_BROADCAST;

		uvh_nmi_mmrx_req = UVH_BIOS_KERNEL_MMR_ALIAS_2;

		uvh_nmi_mmrx_req_shift = 62;

		new_nmi_method_only = true;		/* Newer nmi always valid on UV5+ */

		uvh_nmi_mmrx_req = 0;			/* no request bit to clear */



	} else {

		pr_err("UV:%s:cannot find EVENT_OCCURRED*_EXTIO_INT0\n",

			__func__);

		pr_err("UV:%s:NMI support not available on this system\n", __func__);

		return;

	}



	/* Then find out if new NMI is supported */

	if (likely(uv_read_local_mmr(uvh_nmi_mmrx_supported))) {

	if (new_nmi_method_only || uv_read_local_mmr(uvh_nmi_mmrx_supported)) {

		if (uvh_nmi_mmrx_req)

			uv_write_local_mmr(uvh_nmi_mmrx_req,

						1UL << uvh_nmi_mmrx_req_shift);

		nmi_mmr = uvh_nmi_mmrx;