Commit 1afd9b62 authored by Allen-KH Cheng's avatar Allen-KH Cheng Committed by Matthias Brugger
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arm64: dts: mt8192: Add audio-related nodes 



Add audio-related nodes in audsys for mt8192 SoC.
 - Move audsys node in ascending order.
 - Increase the address range's length from 0x1000 to 0x2000.

Signed-off-by: default avatarAllen-KH Cheng <allen-kh.cheng@mediatek.com>
Link: https://lore.kernel.org/r/20220419025557.22262-3-allen-kh.cheng@mediatek.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent a8bbcf70

arch/arm64/boot/dts/mediatek/mt8192.dtsi

+129 −6
Original line number Diff line number Diff line
@@ -731,6 +731,135 @@ xhci: usb@11200000 { 
			status = "disabled";

		};



		audsys: syscon@11210000 {

			compatible = "mediatek,mt8192-audsys", "syscon";

			reg = <0 0x11210000 0 0x2000>;

			#clock-cells = <1>;



			afe: mt8192-afe-pcm {

				compatible = "mediatek,mt8192-audio";

				interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;

				resets = <&watchdog 17>;

				reset-names = "audiosys";

				mediatek,apmixedsys = <&apmixedsys>;

				mediatek,infracfg = <&infracfg>;

				mediatek,topckgen = <&topckgen>;

				power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;

				clocks = <&audsys CLK_AUD_AFE>,

					 <&audsys CLK_AUD_DAC>,

					 <&audsys CLK_AUD_DAC_PREDIS>,

					 <&audsys CLK_AUD_ADC>,

					 <&audsys CLK_AUD_ADDA6_ADC>,

					 <&audsys CLK_AUD_22M>,

					 <&audsys CLK_AUD_24M>,

					 <&audsys CLK_AUD_APLL_TUNER>,

					 <&audsys CLK_AUD_APLL2_TUNER>,

					 <&audsys CLK_AUD_TDM>,

					 <&audsys CLK_AUD_TML>,

					 <&audsys CLK_AUD_NLE>,

					 <&audsys CLK_AUD_DAC_HIRES>,

					 <&audsys CLK_AUD_ADC_HIRES>,

					 <&audsys CLK_AUD_ADC_HIRES_TML>,

					 <&audsys CLK_AUD_ADDA6_ADC_HIRES>,

					 <&audsys CLK_AUD_3RD_DAC>,

					 <&audsys CLK_AUD_3RD_DAC_PREDIS>,

					 <&audsys CLK_AUD_3RD_DAC_TML>,

					 <&audsys CLK_AUD_3RD_DAC_HIRES>,

					 <&infracfg CLK_INFRA_AUDIO>,

					 <&infracfg CLK_INFRA_AUDIO_26M_B>,

					 <&topckgen CLK_TOP_AUDIO_SEL>,

					 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,

					 <&topckgen CLK_TOP_MAINPLL_D4_D4>,

					 <&topckgen CLK_TOP_AUD_1_SEL>,

					 <&topckgen CLK_TOP_APLL1>,

					 <&topckgen CLK_TOP_AUD_2_SEL>,

					 <&topckgen CLK_TOP_APLL2>,

					 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,

					 <&topckgen CLK_TOP_APLL1_D4>,

					 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,

					 <&topckgen CLK_TOP_APLL2_D4>,

					 <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,

					 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,

					 <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,

					 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,

					 <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,

					 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,

					 <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,

					 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,

					 <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,

					 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,

					 <&topckgen CLK_TOP_APLL12_DIV0>,

					 <&topckgen CLK_TOP_APLL12_DIV1>,

					 <&topckgen CLK_TOP_APLL12_DIV2>,

					 <&topckgen CLK_TOP_APLL12_DIV3>,

					 <&topckgen CLK_TOP_APLL12_DIV4>,

					 <&topckgen CLK_TOP_APLL12_DIVB>,

					 <&topckgen CLK_TOP_APLL12_DIV5>,

					 <&topckgen CLK_TOP_APLL12_DIV6>,

					 <&topckgen CLK_TOP_APLL12_DIV7>,

					 <&topckgen CLK_TOP_APLL12_DIV8>,

					 <&topckgen CLK_TOP_APLL12_DIV9>,

					 <&topckgen CLK_TOP_AUDIO_H_SEL>,

					 <&clk26m>;

				clock-names = "aud_afe_clk",

					      "aud_dac_clk",

					      "aud_dac_predis_clk",

					      "aud_adc_clk",

					      "aud_adda6_adc_clk",

					      "aud_apll22m_clk",

					      "aud_apll24m_clk",

					      "aud_apll1_tuner_clk",

					      "aud_apll2_tuner_clk",

					      "aud_tdm_clk",

					      "aud_tml_clk",

					      "aud_nle",

					      "aud_dac_hires_clk",

					      "aud_adc_hires_clk",

					      "aud_adc_hires_tml",

					      "aud_adda6_adc_hires_clk",

					      "aud_3rd_dac_clk",

					      "aud_3rd_dac_predis_clk",

					      "aud_3rd_dac_tml",

					      "aud_3rd_dac_hires_clk",

					      "aud_infra_clk",

					      "aud_infra_26m_clk",

					      "top_mux_audio",

					      "top_mux_audio_int",

					      "top_mainpll_d4_d4",

					      "top_mux_aud_1",

					      "top_apll1_ck",

					      "top_mux_aud_2",

					      "top_apll2_ck",

					      "top_mux_aud_eng1",

					      "top_apll1_d4",

					      "top_mux_aud_eng2",

					      "top_apll2_d4",

					      "top_i2s0_m_sel",

					      "top_i2s1_m_sel",

					      "top_i2s2_m_sel",

					      "top_i2s3_m_sel",

					      "top_i2s4_m_sel",

					      "top_i2s5_m_sel",

					      "top_i2s6_m_sel",

					      "top_i2s7_m_sel",

					      "top_i2s8_m_sel",

					      "top_i2s9_m_sel",

					      "top_apll12_div0",

					      "top_apll12_div1",

					      "top_apll12_div2",

					      "top_apll12_div3",

					      "top_apll12_div4",

					      "top_apll12_divb",

					      "top_apll12_div5",

					      "top_apll12_div6",

					      "top_apll12_div7",

					      "top_apll12_div8",

					      "top_apll12_div9",

					      "top_mux_audio_h",

					      "top_clk26m_clk";

			};

		};



		pcie: pcie@11230000 {

			compatible = "mediatek,mt8192-pcie";

			device_type = "pci";
@@ -781,12 +910,6 @@ nor_flash: spi@11234000 { 
			status = "disabled";

		};



		audsys: clock-controller@11210000 {

			compatible = "mediatek,mt8192-audsys", "syscon";

			reg = <0 0x11210000 0 0x1000>;

			#clock-cells = <1>;

		};



		efuse: efuse@11c10000 {

			compatible = "mediatek,efuse";

			reg = <0 0x11c10000 0 0x1000>;