Commit 1b2dc99e authored Jan 18, 2022 by Hawking Zhang Committed by Alex Deucher Jan 25, 2022

drm/amdgpu: switch to amdgpu_sriov_rreg/wreg



Instead of ip specific implementation for rlcg
indirect register access

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Zhou, Peng Ju <PengJu.Zhou@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 5d447e29

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -566,7 +566,7 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
		adev->gfx.rlc.funcs &&
		adev->gfx.rlc.funcs->is_rlcg_access_range) {
		if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
		return adev->gfx.rlc.funcs->sriov_wreg(adev, reg, v, 0, 0);
		return amdgpu_sriov_wreg(adev, reg, v, 0, 0);
		} else if ((reg * 4) >= adev->rmmio_size) {
		adev->pcie_wreg(adev, reg * 4, v);
		} else {

drivers/gpu/drm/amd/amdgpu/soc15_common.h

+4 −4

Original line number	Diff line number	Diff line
		@@ -28,13 +28,13 @@
		#define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)

		#define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \
		((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->sriov_wreg) ? \
		adev->gfx.rlc.funcs->sriov_wreg(adev, reg, value, flag, hwip) : \
		((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \
		amdgpu_sriov_wreg(adev, reg, value, flag, hwip) : \
		WREG32(reg, value))

		#define __RREG32_SOC15_RLC__(reg, flag, hwip) \
		((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->sriov_rreg) ? \
		adev->gfx.rlc.funcs->sriov_rreg(adev, reg, flag, hwip) : \
		((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \
		amdgpu_sriov_rreg(adev, reg, flag, hwip) : \
		RREG32(reg))

		#define WREG32_FIELD15(ip, idx, reg, field, val) \