Commit 1b5d0e7e authored by Ilya Bakoulin's avatar Ilya Bakoulin Committed by Alex Deucher
Browse files

drm/amd/display: Speed up DML fast_validate path 



[Why]
Iterating over every voltage state when we need to validate thousands of
configurations all at once (i.e. display hotplug) can take a significant
amount of time.

[How]
Check just the highest voltage state when fast_validate is true to
verify whether the configuration can work at all, then do a proper
validation including all voltage states later when fast_validate is false.

Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: default avatarIlya Bakoulin <Ilya.Bakoulin@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b8ff7e08

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+2 −0
Original line number Diff line number Diff line
@@ -1551,6 +1551,7 @@ bool dcn32_internal_validate_bw(struct dc *dc, 
		context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =

			dm_prefetch_support_fclk_and_stutter;



		context->bw_ctx.dml.validate_max_state = fast_validate;

		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);



		/* Last attempt with Prefetch mode 2 (dm_prefetch_support_stutter == 3) */
@@ -1559,6 +1560,7 @@ bool dcn32_internal_validate_bw(struct dc *dc, 
				dm_prefetch_support_stutter;

			vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);

		}

		context->bw_ctx.dml.validate_max_state = false;



		if (vlevel < context->bw_ctx.dml.soc.num_states) {

			memset(split, 0, sizeof(split));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

+20 −17
Original line number Diff line number Diff line
@@ -1707,7 +1707,7 @@ static void mode_support_configuration(struct vba_vars_st *v, 
void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)

{

	struct vba_vars_st *v = &mode_lib->vba;

	int i, j;

	int i, j, start_state;

	unsigned int k, m;

	unsigned int MaximumMPCCombine;

	unsigned int NumberOfNonCombinedSurfaceOfMaximumBandwidth;
@@ -1720,7 +1720,10 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
#endif



	/*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/



	if (mode_lib->validate_max_state)

		start_state = v->soc.num_states - 1;

	else

		start_state = 0;

	/*Scale Ratio, taps Support Check*/



	mode_lib->vba.ScaleRatioAndTapsSupport = true;
@@ -2009,7 +2012,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
	mode_lib->vba.MPCCombineMethodIncompatible = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsNeededForPStateChangeAndVoltage

			&& v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsPossible;



	for (i = 0; i < v->soc.num_states; i++) {

	for (i = start_state; i < v->soc.num_states; i++) {

		for (j = 0; j < 2; j++) {

			mode_lib->vba.TotalNumberOfActiveDPP[i][j] = 0;

			mode_lib->vba.TotalAvailablePipesSupport[i][j] = true;
@@ -2286,7 +2289,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
		}

	}



	for (i = 0; i < v->soc.num_states; ++i) {

	for (i = start_state; i < v->soc.num_states; ++i) {

		mode_lib->vba.ExceededMultistreamSlots[i] = false;

		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {

			if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == k) {
@@ -2386,7 +2389,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
		}

	}



	for (i = 0; i < v->soc.num_states; ++i) {

	for (i = start_state; i < v->soc.num_states; ++i) {

		mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] = false;

		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {

			if (mode_lib->vba.BlendingAndTiming[k] == k
@@ -2403,7 +2406,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
		}

	}



	for (i = 0; i < v->soc.num_states; ++i) {

	for (i = start_state; i < v->soc.num_states; ++i) {

		mode_lib->vba.ODMCombine2To1SupportCheckOK[i] = true;

		mode_lib->vba.ODMCombine4To1SupportCheckOK[i] = true;

		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
@@ -2421,7 +2424,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
		}

	}



	for (i = 0; i < v->soc.num_states; i++) {

	for (i = start_state; i < v->soc.num_states; i++) {

		mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = false;

		for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {

			if (mode_lib->vba.BlendingAndTiming[k] == k) {
@@ -2458,7 +2461,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
	/* Check DSC Unit and Slices Support */

	v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = 0;



	for (i = 0; i < v->soc.num_states; ++i) {

	for (i = start_state; i < v->soc.num_states; ++i) {

		mode_lib->vba.NotEnoughDSCUnits[i] = false;

		mode_lib->vba.NotEnoughDSCSlices[i] = false;

		v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = 0;
@@ -2493,7 +2496,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
	}



	/*DSC Delay per state*/

	for (i = 0; i < v->soc.num_states; ++i) {

	for (i = start_state; i < v->soc.num_states; ++i) {

		for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {

			mode_lib->vba.DSCDelayPerState[i][k] = dml32_DSCDelayRequirement(

					mode_lib->vba.RequiresDSC[i][k], mode_lib->vba.ODMCombineEnablePerState[i][k],
@@ -2520,7 +2523,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 


	//Calculate Swath, DET Configuration, DCFCLKDeepSleep

	//

	for (i = 0; i < (int) v->soc.num_states; ++i) {

	for (i = start_state; i < (int) v->soc.num_states; ++i) {

		for (j = 0; j <= 1; ++j) {

			for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {

				mode_lib->vba.RequiredDPPCLKThisState[k] = mode_lib->vba.RequiredDPPCLK[i][j][k];
@@ -2655,7 +2658,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
			mode_lib->vba.SurfaceSizeInMALL,

			&mode_lib->vba.ExceededMALLSize);



	for (i = 0; i < v->soc.num_states; i++) {

	for (i = start_state; i < v->soc.num_states; i++) {

		for (j = 0; j < 2; j++) {

			for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {

				mode_lib->vba.swath_width_luma_ub_this_state[k] =
@@ -2882,7 +2885,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
	}



	//Calculate Return BW

	for (i = 0; i < (int) v->soc.num_states; ++i) {

	for (i = start_state; i < (int) v->soc.num_states; ++i) {

		for (j = 0; j <= 1; ++j) {

			for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {

				if (mode_lib->vba.BlendingAndTiming[k] == k) {
@@ -2961,7 +2964,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
			&mode_lib->vba.MinPrefetchMode,

			&mode_lib->vba.MaxPrefetchMode);



	for (i = 0; i < (int) v->soc.num_states; ++i) {

	for (i = start_state; i < (int) v->soc.num_states; ++i) {

		for (j = 0; j <= 1; ++j)

			mode_lib->vba.DCFCLKState[i][j] = mode_lib->vba.DCFCLKPerState[i];

	}
@@ -3083,7 +3086,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
				mode_lib->vba.DCFCLKState);

	} // UseMinimumRequiredDCFCLK == true



	for (i = 0; i < (int) v->soc.num_states; ++i) {

	for (i = start_state; i < (int) v->soc.num_states; ++i) {

		for (j = 0; j <= 1; ++j) {

			mode_lib->vba.ReturnBWPerState[i][j] = dml32_get_return_bw_mbps(&mode_lib->vba.soc, i,

					mode_lib->vba.HostVMEnable, mode_lib->vba.DCFCLKState[i][j],
@@ -3092,7 +3095,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
	}



	//Re-ordering Buffer Support Check

	for (i = 0; i < (int) v->soc.num_states; ++i) {

	for (i = start_state; i < (int) v->soc.num_states; ++i) {

		for (j = 0; j <= 1; ++j) {

			if ((mode_lib->vba.ROBBufferSizeInKByte - mode_lib->vba.PixelChunkSizeInKByte) * 1024

					/ mode_lib->vba.ReturnBWPerState[i][j]
@@ -3114,7 +3117,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
				+ mode_lib->vba.ReadBandwidthChroma[k];

	}



	for (i = 0; i < (int) v->soc.num_states; ++i) {

	for (i = start_state; i < (int) v->soc.num_states; ++i) {

		for (j = 0; j <= 1; ++j) {

			mode_lib->vba.MaxTotalVerticalActiveAvailableBandwidth[i][j] =

				dml_min3(mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLKState[i][j]
@@ -3138,7 +3141,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 


	/* Prefetch Check */



	for (i = 0; i < (int) v->soc.num_states; ++i) {

	for (i = start_state; i < (int) v->soc.num_states; ++i) {

		for (j = 0; j <= 1; ++j) {



			mode_lib->vba.TimeCalc = 24 / mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j];

drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h

+1 −0
Original line number Diff line number Diff line
@@ -91,6 +91,7 @@ struct display_mode_lib { 
	struct dal_logger *logger;

	struct dml_funcs funcs;

	struct _vcs_dpi_display_e2e_pipe_params_st dml_pipe_state[6];

	bool validate_max_state;

};



void dml_init_instance(struct display_mode_lib *lib,