Unverified Commit 1b84450e authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'amlogic-arm64-dt-for-v6.5' of... 

Merge tag 'amlogic-arm64-dt-for-v6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt

Amlogic ARM64 DT changes for v6.4:
- Introduce initial DT for Amlogic C4 SoC based AW409
- add missing cache properties

* tag 'amlogic-arm64-dt-for-v6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
  arm64: dts: add support for C3 based Amlogic AW409
  arm64: dts: amlogic: add missing cache properties
  dt-bindings: arm: amlogic: add C3 bindings

Link: https://lore.kernel.org/r/37e5de2f-47f1-a3f3-f1e4-4a304192e556@linaro.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 705ebd77 02310be6

Documentation/devicetree/bindings/arm/amlogic.yaml

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@@ -4,7 +4,7 @@ 
$id: http://devicetree.org/schemas/arm/amlogic.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic MesonX

title: Amlogic SoC based Platforms



maintainers:

  - Kevin Hilman <khilman@baylibre.com>
@@ -205,6 +205,13 @@ properties: 
              - amlogic,ad401

          - const: amlogic,a1



      - description: Boards with the Amlogic C3 C302X/C308L SoC

        items:

          - enum:

              - amlogic,aw409

              - amlogic,aw419

          - const: amlogic,c3



      - description: Boards with the Amlogic Meson S4 S805X2 SoC

        items:

          - enum:

arch/arm64/boot/dts/amlogic/Makefile

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# SPDX-License-Identifier: GPL-2.0

dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb

dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb

dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j100.dtb

dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j110-rev-2.dtb

arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright (c) 2021 Amlogic, Inc. All rights reserved.

 */



/dts-v1/;



#include "amlogic-c3.dtsi"



/ {

	model = "Amlogic C302 aw409 Development Board";

	compatible = "amlogic,aw409", "amlogic,c3";

	interrupt-parent = <&gic>;

	#address-cells = <2>;

	#size-cells = <2>;



	aliases {

		serial0 = &uart_b;

	};



	memory@0 {

		device_type = "memory";

		reg = <0x0 0x0 0x0 0x10000000>;

	};

};



&uart_b {

	status = "okay";

};

arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright (c) 2021 Amlogic, Inc. All rights reserved.

 */



#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/gpio/gpio.h>



/ {

	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a35";

			reg = <0x0 0x0>;

			enable-method = "psci";

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a35";

			reg = <0x0 0x1>;

			enable-method = "psci";

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	xtal: xtal-clk {

		compatible = "fixed-clock";

		clock-frequency = <24000000>;

		clock-output-names = "xtal";

		#clock-cells = <0>;

	};



	soc {

		compatible = "simple-bus";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		gic: interrupt-controller@fff01000 {

			compatible = "arm,gic-400";

			#interrupt-cells = <3>;

			#address-cells = <0>;

			interrupt-controller;

			reg = <0x0 0xfff01000 0 0x1000>,

			      <0x0 0xfff02000 0 0x2000>,

			      <0x0 0xfff04000 0 0x2000>,

			      <0x0 0xfff06000 0 0x2000>;

			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

		};



		apb4: bus@fe000000 {

			compatible = "simple-bus";

			reg = <0x0 0xfe000000 0x0 0x480000>;

			#address-cells = <2>;

			#size-cells = <2>;

			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;



			uart_b: serial@7a000 {

				compatible = "amlogic,meson-s4-uart",

					   "amlogic,meson-ao-uart";

				reg = <0x0 0x7a000 0x0 0x18>;

				interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;

				status = "disabled";

				clocks = <&xtal>, <&xtal>, <&xtal>;

				clock-names = "xtal", "pclk", "baud";

			};



		};

	};

};

arch/arm64/boot/dts/amlogic/meson-a1.dtsi

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@@ -37,6 +37,7 @@ cpu1: cpu@1 { 
		l2: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

			cache-unified;

		};

	};