Loading arch/arm/mach-realview/core.c +1 −1 Original line number Diff line number Diff line Loading @@ -50,7 +50,7 @@ #define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET) /* used by entry-macro.S */ /* used by entry-macro.S and platsmp.c */ void __iomem *gic_cpu_base_addr; /* Loading arch/arm/mach-realview/include/mach/board-eb.h +3 −0 Original line number Diff line number Diff line Loading @@ -193,4 +193,7 @@ #define core_tile_a9mp() 0 #endif #define machine_is_realview_eb_mp() \ (machine_is_realview_eb() && (core_tile_eb11mp() || core_tile_a9mp())) #endif /* __ASM_ARCH_BOARD_EB_H */ arch/arm/mach-realview/platsmp.c +16 −25 Original line number Diff line number Diff line Loading @@ -23,6 +23,8 @@ #include <mach/board-pb11mp.h> #include <mach/scu.h> #include "core.h" extern void realview_secondary_startup(void); /* Loading @@ -31,16 +33,20 @@ extern void realview_secondary_startup(void); */ volatile int __cpuinitdata pen_release = -1; static void __iomem *scu_base_addr(void) { if (machine_is_realview_eb_mp()) return __io_address(REALVIEW_EB11MP_SCU_BASE); else if (machine_is_realview_pb11mp()) return __io_address(REALVIEW_TC11MP_SCU_BASE); else return (void __iomem *)0; } static unsigned int __init get_core_count(void) { unsigned int ncores; void __iomem *scu_base = 0; if (machine_is_realview_eb() && (core_tile_eb11mp() || core_tile_a9mp())) scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE); else if (machine_is_realview_pb11mp()) scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE); void __iomem *scu_base = scu_base_addr(); if (scu_base) { ncores = __raw_readl(scu_base + SCU_CONFIG); Loading @@ -57,15 +63,7 @@ static unsigned int __init get_core_count(void) static void scu_enable(void) { u32 scu_ctrl; void __iomem *scu_base; if (machine_is_realview_eb() && (core_tile_eb11mp() || core_tile_a9mp())) scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE); else if (machine_is_realview_pb11mp()) scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE); else BUG(); void __iomem *scu_base = scu_base_addr(); scu_ctrl = __raw_readl(scu_base + SCU_CTRL); scu_ctrl |= 1; Loading @@ -90,11 +88,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) * core (e.g. timer irq), then they will not have been enabled * for us: do so */ if (machine_is_realview_eb() && (core_tile_eb11mp() || core_tile_a9mp())) gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); else if (machine_is_realview_pb11mp()) gic_cpu_init(0, __io_address(REALVIEW_TC11MP_GIC_CPU_BASE)); gic_cpu_init(0, gic_cpu_base_addr); /* * let the primary processor know we're out of the Loading Loading @@ -235,9 +229,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus) * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in * realview_timer_init */ if ((machine_is_realview_eb() && (core_tile_eb11mp() || core_tile_a9mp())) || machine_is_realview_pb11mp()) local_timer_setup(); #endif Loading Loading
arch/arm/mach-realview/core.c +1 −1 Original line number Diff line number Diff line Loading @@ -50,7 +50,7 @@ #define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET) /* used by entry-macro.S */ /* used by entry-macro.S and platsmp.c */ void __iomem *gic_cpu_base_addr; /* Loading
arch/arm/mach-realview/include/mach/board-eb.h +3 −0 Original line number Diff line number Diff line Loading @@ -193,4 +193,7 @@ #define core_tile_a9mp() 0 #endif #define machine_is_realview_eb_mp() \ (machine_is_realview_eb() && (core_tile_eb11mp() || core_tile_a9mp())) #endif /* __ASM_ARCH_BOARD_EB_H */
arch/arm/mach-realview/platsmp.c +16 −25 Original line number Diff line number Diff line Loading @@ -23,6 +23,8 @@ #include <mach/board-pb11mp.h> #include <mach/scu.h> #include "core.h" extern void realview_secondary_startup(void); /* Loading @@ -31,16 +33,20 @@ extern void realview_secondary_startup(void); */ volatile int __cpuinitdata pen_release = -1; static void __iomem *scu_base_addr(void) { if (machine_is_realview_eb_mp()) return __io_address(REALVIEW_EB11MP_SCU_BASE); else if (machine_is_realview_pb11mp()) return __io_address(REALVIEW_TC11MP_SCU_BASE); else return (void __iomem *)0; } static unsigned int __init get_core_count(void) { unsigned int ncores; void __iomem *scu_base = 0; if (machine_is_realview_eb() && (core_tile_eb11mp() || core_tile_a9mp())) scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE); else if (machine_is_realview_pb11mp()) scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE); void __iomem *scu_base = scu_base_addr(); if (scu_base) { ncores = __raw_readl(scu_base + SCU_CONFIG); Loading @@ -57,15 +63,7 @@ static unsigned int __init get_core_count(void) static void scu_enable(void) { u32 scu_ctrl; void __iomem *scu_base; if (machine_is_realview_eb() && (core_tile_eb11mp() || core_tile_a9mp())) scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE); else if (machine_is_realview_pb11mp()) scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE); else BUG(); void __iomem *scu_base = scu_base_addr(); scu_ctrl = __raw_readl(scu_base + SCU_CTRL); scu_ctrl |= 1; Loading @@ -90,11 +88,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) * core (e.g. timer irq), then they will not have been enabled * for us: do so */ if (machine_is_realview_eb() && (core_tile_eb11mp() || core_tile_a9mp())) gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); else if (machine_is_realview_pb11mp()) gic_cpu_init(0, __io_address(REALVIEW_TC11MP_GIC_CPU_BASE)); gic_cpu_init(0, gic_cpu_base_addr); /* * let the primary processor know we're out of the Loading Loading @@ -235,9 +229,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus) * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in * realview_timer_init */ if ((machine_is_realview_eb() && (core_tile_eb11mp() || core_tile_a9mp())) || machine_is_realview_pb11mp()) local_timer_setup(); #endif Loading