Commit 1c3439f2 authored by Rafał Miłecki's avatar Rafał Miłecki Committed by Dave Airlie
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drm/radeon/hdmi: update modesetting 



Signed-off-by: default avatarRafał Miłecki <zajec5@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent e55d3e6c

drivers/gpu/drm/radeon/evergreen_hdmi.c

+32 −11
Original line number Diff line number Diff line
@@ -158,30 +158,51 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode 


	r600_audio_set_clock(encoder, mode->clock);



	WREG32(HDMI_VBI_PACKET_CONTROL + offset,

	       HDMI_NULL_SEND); /* send null packets when required */



	WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);

	WREG32(HDMI_GC + offset, 0x0);



	/* Send audio packets */

	WREG32_P(AFMT_AUDIO_PACKET_CONTROL + offset,

		 AFMT_AUDIO_SAMPLE_SEND, ~AFMT_AUDIO_SAMPLE_SEND);

	WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,

	       HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */

	       HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */



	WREG32(HDMI_ACR_PACKET_CONTROL + offset, 0x1000);

	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,

	       AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */

	       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */



	evergreen_hdmi_update_ACR(encoder, mode->clock);

	WREG32(HDMI_ACR_PACKET_CONTROL + offset,

	       HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */

	       HDMI_ACR_SOURCE); /* select SW CTS value */



	WREG32(HDMI_VBI_PACKET_CONTROL + offset,

	       HDMI_NULL_SEND | /* send null packets when required */

	       HDMI_GC_SEND | /* send general control packets */

	       HDMI_GC_CONT); /* send general control packets every frame */



	WREG32(HDMI_INFOFRAME_CONTROL0 + offset,

	       HDMI_AVI_INFO_SEND | /* enable AVI info frames */

	       HDMI_AVI_INFO_CONT | /* send AVI info frames every frame/field */

	       HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */

	       HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */



	WREG32(HDMI_INFOFRAME_CONTROL0 + offset, 0x13);

	WREG32(AFMT_INFOFRAME_CONTROL0 + offset,

	       AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */



	WREG32(HDMI_INFOFRAME_CONTROL1 + offset, 0x202);

	WREG32(HDMI_INFOFRAME_CONTROL1 + offset,

	       HDMI_AVI_INFO_LINE(2) | /* anything other than 0 */

	       HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */



	WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */



	evergreen_hdmi_videoinfoframe(encoder, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

				      0, 0, 0, 0, 0, 0);



	evergreen_hdmi_update_ACR(encoder, mode->clock);



	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */

	WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);

	WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);

	WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);

	WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);



	/* audio packets per line, does anyone know how to calc this ? */

	WREG32_P(AFMT_AUDIO_PACKET_CONTROL + offset, 0x00040000, ~0x001F0000);

}

drivers/gpu/drm/radeon/r600_hdmi.c

+38 −15
Original line number Diff line number Diff line
@@ -324,28 +324,54 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod 


	r600_audio_set_clock(encoder, mode->clock);



	WREG32(HDMI0_VBI_PACKET_CONTROL + offset,

	       HDMI0_NULL_SEND); /* send null packets when required */



	WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);

	WREG32(HDMI0_GC + offset, 0x0);



	/* Send audio packets */

	if (ASIC_IS_DCE32(rdev))

		WREG32_P(AFMT_AUDIO_PACKET_CONTROL + offset,

			 AFMT_AUDIO_SAMPLE_SEND, ~AFMT_AUDIO_SAMPLE_SEND);

	else

		WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,

			 HDMI0_AUDIO_SAMPLE_SEND, ~HDMI0_AUDIO_SAMPLE_SEND);

	if (ASIC_IS_DCE32(rdev)) {

		WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,

		       HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */

		       HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */

		WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,

		       AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */

		       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */

	} else {

		WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,

		       HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */

		       HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */

		       HDMI0_AUDIO_SEND_MAX_PACKETS | /* send NULL packets if no audio is available */

		       HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */

		       HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */

	}



	WREG32(HDMI0_ACR_PACKET_CONTROL + offset, 0x1000);

	WREG32(HDMI0_ACR_PACKET_CONTROL + offset,

	       HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */

	       HDMI0_ACR_SOURCE); /* select SW CTS value */



	r600_hdmi_update_ACR(encoder, mode->clock);

	WREG32(HDMI0_VBI_PACKET_CONTROL + offset,

	       HDMI0_NULL_SEND | /* send null packets when required */

	       HDMI0_GC_SEND | /* send general control packets */

	       HDMI0_GC_CONT); /* send general control packets every frame */



	WREG32(HDMI0_INFOFRAME_CONTROL0 + offset, 0x13);

	/* TODO: HDMI0_AUDIO_INFO_UPDATE */

	WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,

	       HDMI0_AVI_INFO_SEND | /* enable AVI info frames */

	       HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */

	       HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */

	       HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */



	WREG32(HDMI0_INFOFRAME_CONTROL1 + offset, 0x202);

	WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,

	       HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */

	       HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */



	WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */



	r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0,

		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);



	r600_hdmi_update_ACR(encoder, mode->clock);



	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */

	WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);

	WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
@@ -353,9 +379,6 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod 
	WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);



	r600_hdmi_audio_workaround(encoder);



	/* audio packets per line, does anyone know how to calc this ? */

	WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, 0x00040000, ~0x001F0000);

}



/*