Commit 1c465565 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

Merge branch 'pm-sr' of... 

Merge branch 'pm-sr' of ssh://master.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into omap-for-linus
parents f400c82e b35cecf9

arch/arm/mach-omap2/Makefile

+8 −3
Original line number Diff line number Diff line
@@ -18,6 +18,8 @@ obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) 


obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o



obj-$(CONFIG_TWL4030_CORE) += omap_twl.o



# SMP support ONLY available for OMAP4

obj-$(CONFIG_SMP)			+= omap-smp.o omap-headsmp.o

obj-$(CONFIG_LOCAL_TIMERS)		+= timer-mpu.o
@@ -57,10 +59,13 @@ endif 
# Power Management

ifeq ($(CONFIG_PM),y)

obj-$(CONFIG_ARCH_OMAP2)		+= pm24xx.o

obj-$(CONFIG_ARCH_OMAP2)		+= sleep24xx.o pm_bus.o

obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o cpuidle34xx.o pm_bus.o

obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o pm_bus.o

obj-$(CONFIG_ARCH_OMAP2)		+= sleep24xx.o pm_bus.o voltage.o

obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o voltage.o \

					   cpuidle34xx.o pm_bus.o

obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o voltage.o pm_bus.o

obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o

obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o

obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)	+= smartreflex-class3.o



AFLAGS_sleep24xx.o			:=-Wa,-march=armv6

AFLAGS_sleep34xx.o			:=-Wa,-march=armv7-a

arch/arm/mach-omap2/control.h

+29 −0
Original line number Diff line number Diff line
@@ -148,6 +148,15 @@ 
#define OMAP343X_CONTROL_TEST_KEY_11	(OMAP2_CONTROL_GENERAL + 0x00f4)

#define OMAP343X_CONTROL_TEST_KEY_12	(OMAP2_CONTROL_GENERAL + 0x00f8)

#define OMAP343X_CONTROL_TEST_KEY_13	(OMAP2_CONTROL_GENERAL + 0x00fc)

#define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)

#define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)

#define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)

#define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c)

#define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)

#define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124)

#define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)

#define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c)

#define OMAP343X_CONTROL_FUSE_SR        (OMAP2_CONTROL_GENERAL + 0x0130)

#define OMAP343X_CONTROL_IVA2_BOOTADDR	(OMAP2_CONTROL_GENERAL + 0x0190)

#define OMAP343X_CONTROL_IVA2_BOOTMOD	(OMAP2_CONTROL_GENERAL + 0x0194)

#define OMAP343X_CONTROL_DEBOBS(i)	(OMAP2_CONTROL_GENERAL + 0x01B0 \
@@ -164,6 +173,26 @@ 
#define OMAP343X_CONTROL_SRAMLDO5	(OMAP2_CONTROL_GENERAL + 0x02C0)

#define OMAP343X_CONTROL_CSI		(OMAP2_CONTROL_GENERAL + 0x02C4)



/* OMAP3630 only CONTROL_GENERAL register offsets */

#define OMAP3630_CONTROL_FUSE_OPP1G_VDD1        (OMAP2_CONTROL_GENERAL + 0x0110)

#define OMAP3630_CONTROL_FUSE_OPP50_VDD1        (OMAP2_CONTROL_GENERAL + 0x0114)

#define OMAP3630_CONTROL_FUSE_OPP100_VDD1       (OMAP2_CONTROL_GENERAL + 0x0118)

#define OMAP3630_CONTROL_FUSE_OPP120_VDD1       (OMAP2_CONTROL_GENERAL + 0x0120)

#define OMAP3630_CONTROL_FUSE_OPP50_VDD2        (OMAP2_CONTROL_GENERAL + 0x0128)

#define OMAP3630_CONTROL_FUSE_OPP100_VDD2       (OMAP2_CONTROL_GENERAL + 0x012C)



/* OMAP44xx control efuse offsets */

#define OMAP44XX_CONTROL_FUSE_IVA_OPP50		0x22C

#define OMAP44XX_CONTROL_FUSE_IVA_OPP100	0x22F

#define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO	0x232

#define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO	0x235

#define OMAP44XX_CONTROL_FUSE_MPU_OPP50		0x240

#define OMAP44XX_CONTROL_FUSE_MPU_OPP100	0x243

#define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO	0x246

#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO	0x249

#define OMAP44XX_CONTROL_FUSE_CORE_OPP50	0x254

#define OMAP44XX_CONTROL_FUSE_CORE_OPP100	0x257



/* AM35XX only CONTROL_GENERAL register offsets */

#define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)

#define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)

arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

+175 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#include <plat/l4_3xxx.h>

#include <plat/i2c.h>

#include <plat/gpio.h>

#include <plat/smartreflex.h>



#include "omap_hwmod_common_data.h"
@@ -52,6 +53,8 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod; 
static struct omap_hwmod omap3xxx_gpio4_hwmod;

static struct omap_hwmod omap3xxx_gpio5_hwmod;

static struct omap_hwmod omap3xxx_gpio6_hwmod;

static struct omap_hwmod omap34xx_sr1_hwmod;

static struct omap_hwmod omap34xx_sr2_hwmod;



static struct omap_hwmod omap3xxx_dma_system_hwmod;
@@ -262,9 +265,47 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { 
	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* L4 CORE -> SR1 interface */

static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {

	{

		.pa_start	= OMAP34XX_SR1_BASE,

		.pa_end		= OMAP34XX_SR1_BASE + SZ_1K - 1,

		.flags		= ADDR_TYPE_RT,

	},

};



static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {

	.master		= &omap3xxx_l4_core_hwmod,

	.slave		= &omap34xx_sr1_hwmod,

	.clk		= "sr_l4_ick",

	.addr		= omap3_sr1_addr_space,

	.addr_cnt	= ARRAY_SIZE(omap3_sr1_addr_space),

	.user		= OCP_USER_MPU,

};



/* L4 CORE -> SR1 interface */

static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {

	{

		.pa_start	= OMAP34XX_SR2_BASE,

		.pa_end		= OMAP34XX_SR2_BASE + SZ_1K - 1,

		.flags		= ADDR_TYPE_RT,

	},

};



static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {

	.master		= &omap3xxx_l4_core_hwmod,

	.slave		= &omap34xx_sr2_hwmod,

	.clk		= "sr_l4_ick",

	.addr		= omap3_sr2_addr_space,

	.addr_cnt	= ARRAY_SIZE(omap3_sr2_addr_space),

	.user		= OCP_USER_MPU,

};



/* Slave interfaces on the L4_CORE interconnect */

static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {

	&omap3xxx_l3_main__l4_core,

	&omap3_l4_core__sr1,

	&omap3_l4_core__sr2,

};



/* Master interfaces on the L4_CORE interconnect */
@@ -1186,6 +1227,135 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = { 
	.flags		= HWMOD_NO_IDLEST,

};



/* SR common */

static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {

	.clkact_shift	= 20,

};



static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {

	.sysc_offs	= 0x24,

	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),

	.clockact	= CLOCKACT_TEST_ICLK,

	.sysc_fields	= &omap34xx_sr_sysc_fields,

};



static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {

	.name = "smartreflex",

	.sysc = &omap34xx_sr_sysc,

	.rev  = 1,

};



static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {

	.sidle_shift	= 24,

	.enwkup_shift	= 26

};



static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {

	.sysc_offs	= 0x38,

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |

			SYSC_NO_CACHE),

	.sysc_fields	= &omap36xx_sr_sysc_fields,

};



static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {

	.name = "smartreflex",

	.sysc = &omap36xx_sr_sysc,

	.rev  = 2,

};



/* SR1 */

static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {

	&omap3_l4_core__sr1,

};



static struct omap_hwmod omap34xx_sr1_hwmod = {

	.name		= "sr1_hwmod",

	.class		= &omap34xx_smartreflex_hwmod_class,

	.main_clk	= "sr1_fck",

	.vdd_name	= "mpu",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP3430_EN_SR1_SHIFT,

			.module_offs = WKUP_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,

		},

	},

	.slaves		= omap3_sr1_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap3_sr1_slaves),

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |

					CHIP_IS_OMAP3430ES3_0 |

					CHIP_IS_OMAP3430ES3_1),

	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,

};



static struct omap_hwmod omap36xx_sr1_hwmod = {

	.name		= "sr1_hwmod",

	.class		= &omap36xx_smartreflex_hwmod_class,

	.main_clk	= "sr1_fck",

	.vdd_name	= "mpu",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP3430_EN_SR1_SHIFT,

			.module_offs = WKUP_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,

		},

	},

	.slaves		= omap3_sr1_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap3_sr1_slaves),

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),

};



/* SR2 */

static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {

	&omap3_l4_core__sr2,

};



static struct omap_hwmod omap34xx_sr2_hwmod = {

	.name		= "sr2_hwmod",

	.class		= &omap34xx_smartreflex_hwmod_class,

	.main_clk	= "sr2_fck",

	.vdd_name	= "core",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP3430_EN_SR2_SHIFT,

			.module_offs = WKUP_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,

		},

	},

	.slaves		= omap3_sr2_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap3_sr2_slaves),

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |

					CHIP_IS_OMAP3430ES3_0 |

					CHIP_IS_OMAP3430ES3_1),

	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,

};



static struct omap_hwmod omap36xx_sr2_hwmod = {

	.name		= "sr2_hwmod",

	.class		= &omap36xx_smartreflex_hwmod_class,

	.main_clk	= "sr2_fck",

	.vdd_name	= "core",

	.prcm		= {

		.omap2 = {

			.prcm_reg_id = 1,

			.module_bit = OMAP3430_EN_SR2_SHIFT,

			.module_offs = WKUP_MOD,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,

		},

	},

	.slaves		= omap3_sr2_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap3_sr2_slaves),

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),

};



static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {

	&omap3xxx_l3_main_hwmod,

	&omap3xxx_l4_core_hwmod,
@@ -1201,6 +1371,11 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { 
	&omap3xxx_i2c1_hwmod,

	&omap3xxx_i2c2_hwmod,

	&omap3xxx_i2c3_hwmod,

	&omap34xx_sr1_hwmod,

	&omap34xx_sr2_hwmod,

	&omap36xx_sr1_hwmod,

	&omap36xx_sr2_hwmod,





	/* gpio class */

	&omap3xxx_gpio1_hwmod,

arch/arm/mach-omap2/omap_hwmod_44xx_data.c

+168 −0
Original line number Diff line number Diff line
@@ -1842,6 +1842,169 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = { 
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),

};



/*

 * 'smartreflex' class

 * smartreflex module (monitor silicon performance and outputs a measure of

 * performance error)

 */



/* The IP is not compliant to type1 / type2 scheme */

static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {

	.sidle_shift	= 24,

	.enwkup_shift	= 26,

};



static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {

	.sysc_offs	= 0x0038,

	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type_smartreflex,

};



static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {

	.name = "smartreflex",

	.sysc = &omap44xx_smartreflex_sysc,

	.rev  = 2,

};



/* smartreflex_core */

static struct omap_hwmod omap44xx_smartreflex_core_hwmod;

static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {

	{ .irq = 19 + OMAP44XX_IRQ_GIC_START },

};



static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {

	{

		.pa_start	= 0x4a0dd000,

		.pa_end		= 0x4a0dd03f,

		.flags		= ADDR_TYPE_RT

	},

};



/* l4_cfg -> smartreflex_core */

static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {

	.master		= &omap44xx_l4_cfg_hwmod,

	.slave		= &omap44xx_smartreflex_core_hwmod,

	.clk		= "l4_div_ck",

	.addr		= omap44xx_smartreflex_core_addrs,

	.addr_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_addrs),

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* smartreflex_core slave ports */

static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {

	&omap44xx_l4_cfg__smartreflex_core,

};



static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {

	.name		= "smartreflex_core",

	.class		= &omap44xx_smartreflex_hwmod_class,

	.mpu_irqs	= omap44xx_smartreflex_core_irqs,

	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_irqs),

	.main_clk	= "smartreflex_core_fck",

	.vdd_name	= "core",

	.prcm = {

		.omap4 = {

			.clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,

		},

	},

	.slaves		= omap44xx_smartreflex_core_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_slaves),

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),

};



/* smartreflex_iva */

static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;

static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {

	{ .irq = 102 + OMAP44XX_IRQ_GIC_START },

};



static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {

	{

		.pa_start	= 0x4a0db000,

		.pa_end		= 0x4a0db03f,

		.flags		= ADDR_TYPE_RT

	},

};



/* l4_cfg -> smartreflex_iva */

static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {

	.master		= &omap44xx_l4_cfg_hwmod,

	.slave		= &omap44xx_smartreflex_iva_hwmod,

	.clk		= "l4_div_ck",

	.addr		= omap44xx_smartreflex_iva_addrs,

	.addr_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* smartreflex_iva slave ports */

static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {

	&omap44xx_l4_cfg__smartreflex_iva,

};



static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {

	.name		= "smartreflex_iva",

	.class		= &omap44xx_smartreflex_hwmod_class,

	.mpu_irqs	= omap44xx_smartreflex_iva_irqs,

	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),

	.main_clk	= "smartreflex_iva_fck",

	.vdd_name	= "iva",

	.prcm = {

		.omap4 = {

			.clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,

		},

	},

	.slaves		= omap44xx_smartreflex_iva_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),

};



/* smartreflex_mpu */

static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;

static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {

	{ .irq = 18 + OMAP44XX_IRQ_GIC_START },

};



static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {

	{

		.pa_start	= 0x4a0d9000,

		.pa_end		= 0x4a0d903f,

		.flags		= ADDR_TYPE_RT

	},

};



/* l4_cfg -> smartreflex_mpu */

static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {

	.master		= &omap44xx_l4_cfg_hwmod,

	.slave		= &omap44xx_smartreflex_mpu_hwmod,

	.clk		= "l4_div_ck",

	.addr		= omap44xx_smartreflex_mpu_addrs,

	.addr_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* smartreflex_mpu slave ports */

static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {

	&omap44xx_l4_cfg__smartreflex_mpu,

};



static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {

	.name		= "smartreflex_mpu",

	.class		= &omap44xx_smartreflex_hwmod_class,

	.mpu_irqs	= omap44xx_smartreflex_mpu_irqs,

	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),

	.main_clk	= "smartreflex_mpu_fck",

	.vdd_name	= "mpu",

	.prcm = {

		.omap4 = {

			.clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,

		},

	},

	.slaves		= omap44xx_smartreflex_mpu_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),

};



static __initdata struct omap_hwmod *omap44xx_hwmods[] = {

	/* dmm class */

	&omap44xx_dmm_hwmod,
@@ -1903,6 +2066,11 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { 
	&omap44xx_wd_timer2_hwmod,

	&omap44xx_wd_timer3_hwmod,



	/* smartreflex class */

	&omap44xx_smartreflex_core_hwmod,

	&omap44xx_smartreflex_iva_hwmod,

	&omap44xx_smartreflex_mpu_hwmod,



	NULL,

};

arch/arm/mach-omap2/omap_twl.c

0 → 100644
+277 −0
Original line number Diff line number Diff line 
/**

 * OMAP and TWL PMIC specific intializations.

 *

 * Copyright (C) 2010 Texas Instruments Incorporated.

 * Thara Gopinath

 * Copyright (C) 2009 Texas Instruments Incorporated.

 * Nishanth Menon

 * Copyright (C) 2009 Nokia Corporation

 * Paul Walmsley

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */



#include <linux/err.h>

#include <linux/io.h>

#include <linux/kernel.h>

#include <linux/i2c/twl.h>



#include <plat/voltage.h>



#define OMAP3_SRI2C_SLAVE_ADDR		0x12

#define OMAP3_VDD_MPU_SR_CONTROL_REG	0x00

#define OMAP3_VDD_CORE_SR_CONTROL_REG	0x01

#define OMAP3_VP_CONFIG_ERROROFFSET	0x00

#define OMAP3_VP_VSTEPMIN_VSTEPMIN	0x1

#define OMAP3_VP_VSTEPMAX_VSTEPMAX	0x04

#define OMAP3_VP_VLIMITTO_TIMEOUT_US	200



#define OMAP3430_VP1_VLIMITTO_VDDMIN	0x14

#define OMAP3430_VP1_VLIMITTO_VDDMAX	0x42

#define OMAP3430_VP2_VLIMITTO_VDDMIN	0x18

#define OMAP3430_VP2_VLIMITTO_VDDMAX	0x2c



#define OMAP3630_VP1_VLIMITTO_VDDMIN	0x18

#define OMAP3630_VP1_VLIMITTO_VDDMAX	0x3c

#define OMAP3630_VP2_VLIMITTO_VDDMIN	0x18

#define OMAP3630_VP2_VLIMITTO_VDDMAX	0x30



#define OMAP4_SRI2C_SLAVE_ADDR		0x12

#define OMAP4_VDD_MPU_SR_VOLT_REG	0x55

#define OMAP4_VDD_IVA_SR_VOLT_REG	0x5B

#define OMAP4_VDD_CORE_SR_VOLT_REG	0x61



#define OMAP4_VP_CONFIG_ERROROFFSET	0x00

#define OMAP4_VP_VSTEPMIN_VSTEPMIN	0x01

#define OMAP4_VP_VSTEPMAX_VSTEPMAX	0x04

#define OMAP4_VP_VLIMITTO_TIMEOUT_US	200



#define OMAP4_VP_MPU_VLIMITTO_VDDMIN	0xA

#define OMAP4_VP_MPU_VLIMITTO_VDDMAX	0x39

#define OMAP4_VP_IVA_VLIMITTO_VDDMIN	0xA

#define OMAP4_VP_IVA_VLIMITTO_VDDMAX	0x2D

#define OMAP4_VP_CORE_VLIMITTO_VDDMIN	0xA

#define OMAP4_VP_CORE_VLIMITTO_VDDMAX	0x28



static bool is_offset_valid;

static u8 smps_offset;



#define REG_SMPS_OFFSET         0xE0



unsigned long twl4030_vsel_to_uv(const u8 vsel)

{

	return (((vsel * 125) + 6000)) * 100;

}



u8 twl4030_uv_to_vsel(unsigned long uv)

{

	return DIV_ROUND_UP(uv - 600000, 12500);

}



unsigned long twl6030_vsel_to_uv(const u8 vsel)

{

	/*

	 * In TWL6030 depending on the value of SMPS_OFFSET

	 * efuse register the voltage range supported in

	 * standard mode can be either between 0.6V - 1.3V or

	 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse

	 * is programmed to all 0's where as starting from

	 * TWL6030 ES1.1 the efuse is programmed to 1

	 */

	if (!is_offset_valid) {

		twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,

				REG_SMPS_OFFSET);

		is_offset_valid = true;

	}



	/*

	 * There is no specific formula for voltage to vsel

	 * conversion above 1.3V. There are special hardcoded

	 * values for voltages above 1.3V. Currently we are

	 * hardcoding only for 1.35 V which is used for 1GH OPP for

	 * OMAP4430.

	 */

	if (vsel == 0x3A)

		return 1350000;



	if (smps_offset & 0x8)

		return ((((vsel - 1) * 125) + 7000)) * 100;

	else

		return ((((vsel - 1) * 125) + 6000)) * 100;

}



u8 twl6030_uv_to_vsel(unsigned long uv)

{

	/*

	 * In TWL6030 depending on the value of SMPS_OFFSET

	 * efuse register the voltage range supported in

	 * standard mode can be either between 0.6V - 1.3V or

	 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse

	 * is programmed to all 0's where as starting from

	 * TWL6030 ES1.1 the efuse is programmed to 1

	 */

	if (!is_offset_valid) {

		twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,

				REG_SMPS_OFFSET);

		is_offset_valid = true;

	}



	/*

	 * There is no specific formula for voltage to vsel

	 * conversion above 1.3V. There are special hardcoded

	 * values for voltages above 1.3V. Currently we are

	 * hardcoding only for 1.35 V which is used for 1GH OPP for

	 * OMAP4430.

	 */

	if (uv == 1350000)

		return 0x3A;



	if (smps_offset & 0x8)

		return DIV_ROUND_UP(uv - 700000, 12500) + 1;

	else

		return DIV_ROUND_UP(uv - 600000, 12500) + 1;

}



static struct omap_volt_pmic_info omap3_mpu_volt_info = {

	.slew_rate		= 4000,

	.step_size		= 12500,

	.on_volt		= 1200000,

	.onlp_volt		= 1000000,

	.ret_volt		= 975000,

	.off_volt		= 600000,

	.volt_setup_time	= 0xfff,

	.vp_erroroffset		= OMAP3_VP_CONFIG_ERROROFFSET,

	.vp_vstepmin		= OMAP3_VP_VSTEPMIN_VSTEPMIN,

	.vp_vstepmax		= OMAP3_VP_VSTEPMAX_VSTEPMAX,

	.vp_vddmin		= OMAP3430_VP1_VLIMITTO_VDDMIN,

	.vp_vddmax		= OMAP3430_VP1_VLIMITTO_VDDMAX,

	.vp_timeout_us		= OMAP3_VP_VLIMITTO_TIMEOUT_US,

	.i2c_slave_addr		= OMAP3_SRI2C_SLAVE_ADDR,

	.pmic_reg		= OMAP3_VDD_MPU_SR_CONTROL_REG,

	.vsel_to_uv		= twl4030_vsel_to_uv,

	.uv_to_vsel		= twl4030_uv_to_vsel,

};



static struct omap_volt_pmic_info omap3_core_volt_info = {

	.slew_rate		= 4000,

	.step_size		= 12500,

	.on_volt                = 1200000,

	.onlp_volt              = 1000000,

	.ret_volt               = 975000,

	.off_volt               = 600000,

	.volt_setup_time        = 0xfff,

	.vp_erroroffset		= OMAP3_VP_CONFIG_ERROROFFSET,

	.vp_vstepmin		= OMAP3_VP_VSTEPMIN_VSTEPMIN,

	.vp_vstepmax		= OMAP3_VP_VSTEPMAX_VSTEPMAX,

	.vp_vddmin		= OMAP3430_VP2_VLIMITTO_VDDMIN,

	.vp_vddmax		= OMAP3430_VP2_VLIMITTO_VDDMAX,

	.vp_timeout_us		= OMAP3_VP_VLIMITTO_TIMEOUT_US,

	.i2c_slave_addr		= OMAP3_SRI2C_SLAVE_ADDR,

	.pmic_reg		= OMAP3_VDD_CORE_SR_CONTROL_REG,

	.vsel_to_uv		= twl4030_vsel_to_uv,

	.uv_to_vsel		= twl4030_uv_to_vsel,

};



static struct omap_volt_pmic_info omap4_mpu_volt_info = {

	.slew_rate		= 4000,

	.step_size		= 12500,

	.on_volt		= 1350000,

	.onlp_volt		= 1350000,

	.ret_volt		= 837500,

	.off_volt		= 600000,

	.volt_setup_time	= 0,

	.vp_erroroffset		= OMAP4_VP_CONFIG_ERROROFFSET,

	.vp_vstepmin		= OMAP4_VP_VSTEPMIN_VSTEPMIN,

	.vp_vstepmax		= OMAP4_VP_VSTEPMAX_VSTEPMAX,

	.vp_vddmin		= OMAP4_VP_MPU_VLIMITTO_VDDMIN,

	.vp_vddmax		= OMAP4_VP_MPU_VLIMITTO_VDDMAX,

	.vp_timeout_us		= OMAP4_VP_VLIMITTO_TIMEOUT_US,

	.i2c_slave_addr		= OMAP4_SRI2C_SLAVE_ADDR,

	.pmic_reg		= OMAP4_VDD_MPU_SR_VOLT_REG,

	.vsel_to_uv		= twl6030_vsel_to_uv,

	.uv_to_vsel		= twl6030_uv_to_vsel,

};



static struct omap_volt_pmic_info omap4_iva_volt_info = {

	.slew_rate		= 4000,

	.step_size		= 12500,

	.on_volt		= 1100000,

	.onlp_volt		= 1100000,

	.ret_volt		= 837500,

	.off_volt		= 600000,

	.volt_setup_time	= 0,

	.vp_erroroffset		= OMAP4_VP_CONFIG_ERROROFFSET,

	.vp_vstepmin		= OMAP4_VP_VSTEPMIN_VSTEPMIN,

	.vp_vstepmax		= OMAP4_VP_VSTEPMAX_VSTEPMAX,

	.vp_vddmin		= OMAP4_VP_IVA_VLIMITTO_VDDMIN,

	.vp_vddmax		= OMAP4_VP_IVA_VLIMITTO_VDDMAX,

	.vp_timeout_us		= OMAP4_VP_VLIMITTO_TIMEOUT_US,

	.i2c_slave_addr		= OMAP4_SRI2C_SLAVE_ADDR,

	.pmic_reg		= OMAP4_VDD_IVA_SR_VOLT_REG,

	.vsel_to_uv		= twl6030_vsel_to_uv,

	.uv_to_vsel		= twl6030_uv_to_vsel,

};



static struct omap_volt_pmic_info omap4_core_volt_info = {

	.slew_rate		= 4000,

	.step_size		= 12500,

	.on_volt		= 1100000,

	.onlp_volt		= 1100000,

	.ret_volt		= 837500,

	.off_volt		= 600000,

	.volt_setup_time	= 0,

	.vp_erroroffset		= OMAP4_VP_CONFIG_ERROROFFSET,

	.vp_vstepmin		= OMAP4_VP_VSTEPMIN_VSTEPMIN,

	.vp_vstepmax		= OMAP4_VP_VSTEPMAX_VSTEPMAX,

	.vp_vddmin		= OMAP4_VP_CORE_VLIMITTO_VDDMIN,

	.vp_vddmax		= OMAP4_VP_CORE_VLIMITTO_VDDMAX,

	.vp_timeout_us		= OMAP4_VP_VLIMITTO_TIMEOUT_US,

	.i2c_slave_addr		= OMAP4_SRI2C_SLAVE_ADDR,

	.pmic_reg		= OMAP4_VDD_CORE_SR_VOLT_REG,

	.vsel_to_uv		= twl6030_vsel_to_uv,

	.uv_to_vsel		= twl6030_uv_to_vsel,

};



int __init omap4_twl_init(void)

{

	struct voltagedomain *voltdm;



	if (!cpu_is_omap44xx())

		return -ENODEV;



	voltdm = omap_voltage_domain_lookup("mpu");

	omap_voltage_register_pmic(voltdm, &omap4_mpu_volt_info);



	voltdm = omap_voltage_domain_lookup("iva");

	omap_voltage_register_pmic(voltdm, &omap4_iva_volt_info);



	voltdm = omap_voltage_domain_lookup("core");

	omap_voltage_register_pmic(voltdm, &omap4_core_volt_info);



	return 0;

}



int __init omap3_twl_init(void)

{

	struct voltagedomain *voltdm;



	if (!cpu_is_omap34xx())

		return -ENODEV;



	if (cpu_is_omap3630()) {

		omap3_mpu_volt_info.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;

		omap3_mpu_volt_info.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;

		omap3_core_volt_info.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;

		omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;

	}



	voltdm = omap_voltage_domain_lookup("mpu");

	omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info);



	voltdm = omap_voltage_domain_lookup("core");

	omap_voltage_register_pmic(voltdm, &omap3_core_volt_info);



	return 0;

}