Commit 1c534671 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: rework GPU reset on cayman/TN 



Update the code to better match the recommended
programming sequence for soft reset.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 187e3593

drivers/gpu/drm/radeon/si.c

+90 −92
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); 
extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);

extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);

extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);

extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);



/* get temperature in millidegrees */

int si_get_temp(struct radeon_device *rdev)
@@ -2126,71 +2127,41 @@ bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 
	return radeon_ring_test_lockup(rdev, ring);

}



static void si_gpu_soft_reset_gfx(struct radeon_device *rdev)

static int si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)

{

	u32 grbm_reset = 0;

	struct evergreen_mc_save save;

	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;

	u32 tmp;

	int ret = 0;



	if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))

		return;



	dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",

		RREG32(GRBM_STATUS));

	dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",

		RREG32(GRBM_STATUS2));

	dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",

		RREG32(GRBM_STATUS_SE0));

	dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",

		RREG32(GRBM_STATUS_SE1));

	dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",

		RREG32(SRBM_STATUS));

		reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP);



	/* Disable CP parsing/prefetching */

	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);

	if (RREG32(DMA_STATUS_REG) & DMA_IDLE)

		reset_mask &= ~RADEON_RESET_DMA;



	/* reset all the gfx blocks */

	grbm_reset = (SOFT_RESET_CP |

		      SOFT_RESET_CB |

		      SOFT_RESET_DB |

		      SOFT_RESET_GDS |

		      SOFT_RESET_PA |

		      SOFT_RESET_SC |

		      SOFT_RESET_BCI |

		      SOFT_RESET_SPI |

		      SOFT_RESET_SX |

		      SOFT_RESET_TC |

		      SOFT_RESET_TA |

		      SOFT_RESET_VGT |

		      SOFT_RESET_IA);

	if (reset_mask == 0)

		return 0;



	dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);

	WREG32(GRBM_SOFT_RESET, grbm_reset);

	(void)RREG32(GRBM_SOFT_RESET);

	udelay(50);

	WREG32(GRBM_SOFT_RESET, 0);

	(void)RREG32(GRBM_SOFT_RESET);

	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);



	dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",

		RREG32(GRBM_STATUS));

	dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",

		RREG32(GRBM_STATUS2));

	dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",

		RREG32(GRBM_STATUS_SE0));

	dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",

		RREG32(GRBM_STATUS_SE1));

	dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",

		RREG32(SRBM_STATUS));

}

	evergreen_print_gpu_status_regs(rdev);

	dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",

		 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));

	dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",

		 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));



static void si_gpu_soft_reset_dma(struct radeon_device *rdev)

{

	u32 tmp;

	r600_set_bios_scratch_engine_hung(rdev, true);



	if (RREG32(DMA_STATUS_REG) & DMA_IDLE)

		return;

	evergreen_mc_stop(rdev, &save);

	if (evergreen_mc_wait_for_idle(rdev)) {

		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");

	}



	dev_info(rdev->dev, "  DMA_STATUS_REG   = 0x%08X\n",

		RREG32(DMA_STATUS_REG));

	/* Disable CP parsing/prefetching */

	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);



	if (reset_mask & RADEON_RESET_DMA) {

		/* dma0 */

		tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);

		tmp &= ~DMA_RB_ENABLE;
@@ -2200,57 +2171,83 @@ static void si_gpu_soft_reset_dma(struct radeon_device *rdev) 
		tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

		tmp &= ~DMA_RB_ENABLE;

		WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);



	/* Reset dma */

	WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);

	RREG32(SRBM_SOFT_RESET);

	udelay(50);

	WREG32(SRBM_SOFT_RESET, 0);



	dev_info(rdev->dev, "  DMA_STATUS_REG   = 0x%08X\n",

		RREG32(DMA_STATUS_REG));

	}



static int si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)

{

	struct evergreen_mc_save save;

	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {

		grbm_soft_reset = SOFT_RESET_CB |

			SOFT_RESET_DB |

			SOFT_RESET_GDS |

			SOFT_RESET_PA |

			SOFT_RESET_SC |

			SOFT_RESET_BCI |

			SOFT_RESET_SPI |

			SOFT_RESET_SX |

			SOFT_RESET_TC |

			SOFT_RESET_TA |

			SOFT_RESET_VGT |

			SOFT_RESET_IA;

	}



	if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))

		reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);

	if (reset_mask & RADEON_RESET_CP) {

		grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;



	if (RREG32(DMA_STATUS_REG) & DMA_IDLE)

		reset_mask &= ~RADEON_RESET_DMA;

		srbm_soft_reset |= SOFT_RESET_GRBM;

	}



	if (reset_mask == 0)

		return 0;

	if (reset_mask & RADEON_RESET_DMA)

		srbm_soft_reset |= SOFT_RESET_DMA | SOFT_RESET_DMA1;



	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);

	if (grbm_soft_reset) {

		tmp = RREG32(GRBM_SOFT_RESET);

		tmp |= grbm_soft_reset;

		dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);

		WREG32(GRBM_SOFT_RESET, tmp);

		tmp = RREG32(GRBM_SOFT_RESET);



	dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",

		 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));

	dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",

		 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));



	r600_set_bios_scratch_engine_hung(rdev, true);

		udelay(50);



	evergreen_mc_stop(rdev, &save);

	if (radeon_mc_wait_for_idle(rdev)) {

		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");

		tmp &= ~grbm_soft_reset;

		WREG32(GRBM_SOFT_RESET, tmp);

		tmp = RREG32(GRBM_SOFT_RESET);

	}



	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))

		si_gpu_soft_reset_gfx(rdev);

	if (srbm_soft_reset) {

		tmp = RREG32(SRBM_SOFT_RESET);

		tmp |= srbm_soft_reset;

		dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);

		WREG32(SRBM_SOFT_RESET, tmp);

		tmp = RREG32(SRBM_SOFT_RESET);



	if (reset_mask & RADEON_RESET_DMA)

		si_gpu_soft_reset_dma(rdev);

		udelay(50);



		tmp &= ~srbm_soft_reset;

		WREG32(SRBM_SOFT_RESET, tmp);

		tmp = RREG32(SRBM_SOFT_RESET);

	}



	/* Wait a little for things to settle down */

	udelay(50);



	evergreen_mc_resume(rdev, &save);

	udelay(50);



#if 0

	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {

		if (RREG32(GRBM_STATUS) & GUI_ACTIVE)

			ret = -EAGAIN;

	}



	if (reset_mask & RADEON_RESET_DMA) {

		if (!(RREG32(DMA_STATUS_REG) & DMA_IDLE))

			ret = -EAGAIN;

	}

#endif



	if (!ret)

		r600_set_bios_scratch_engine_hung(rdev, false);



	evergreen_print_gpu_status_regs(rdev);



	return 0;

}
@@ -2258,7 +2255,8 @@ int si_asic_reset(struct radeon_device *rdev) 
{

	return si_gpu_soft_reset(rdev, (RADEON_RESET_GFX |

					RADEON_RESET_COMPUTE |

					RADEON_RESET_DMA));

					RADEON_RESET_DMA |

					RADEON_RESET_CP));

}



/* MC */