Commit 1c6e527d authored by Imre Deak's avatar Imre Deak
Browse files

drm/i915/dp: Move intel_dp_set_signal_levels() to intel_dp_link_training.c 



intel_dp_set_signal_levels() is needed for link training, so move it to
intel_dp_link_training.c.

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201229172201.4155327-1-imre.deak@intel.com
parent d5a0d4b9

drivers/gpu/drm/i915/display/intel_dp.c

+0 −18
Original line number Diff line number Diff line
@@ -5060,24 +5060,6 @@ ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp, 
	intel_de_posting_read(dev_priv, intel_dp->output_reg);

}



void intel_dp_set_signal_levels(struct intel_dp *intel_dp,

				const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	u8 train_set = intel_dp->train_set[0];



	drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",

		    train_set & DP_TRAIN_VOLTAGE_SWING_MASK,

		    train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");

	drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",

		    (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>

		    DP_TRAIN_PRE_EMPHASIS_SHIFT,

		    train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?

		    " (max)" : "");



	intel_dp->set_signal_levels(intel_dp, crtc_state);

}



void

intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,

				       const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp.h

+0 −3
Original line number Diff line number Diff line
@@ -96,9 +96,6 @@ void 
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,

				       const struct intel_crtc_state *crtc_state,

				       u8 dp_train_pat);

void

intel_dp_set_signal_levels(struct intel_dp *intel_dp,

			   const struct intel_crtc_state *crtc_state);

void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,

			   u8 *link_bw, u8 *rate_select);

bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

+18 −0
Original line number Diff line number Diff line
@@ -334,6 +334,24 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, 
	return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;

}



void intel_dp_set_signal_levels(struct intel_dp *intel_dp,

				const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	u8 train_set = intel_dp->train_set[0];



	drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",

		    train_set & DP_TRAIN_VOLTAGE_SWING_MASK,

		    train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");

	drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",

		    (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>

		    DP_TRAIN_PRE_EMPHASIS_SHIFT,

		    train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?

		    " (max)" : "");



	intel_dp->set_signal_levels(intel_dp, crtc_state);

}



static bool

intel_dp_reset_link_train(struct intel_dp *intel_dp,

			  const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

+2 −0
Original line number Diff line number Diff line
@@ -17,6 +17,8 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp, 
			       const struct intel_crtc_state *crtc_state,

			       enum drm_dp_phy dp_phy,

			       const u8 link_status[DP_LINK_STATUS_SIZE]);

void intel_dp_set_signal_levels(struct intel_dp *intel_dp,

				const struct intel_crtc_state *crtc_state);

void intel_dp_start_link_train(struct intel_dp *intel_dp,

			       const struct intel_crtc_state *crtc_state);

void intel_dp_stop_link_train(struct intel_dp *intel_dp,