Commit 1cf49dea authored by Wenjing Liu's avatar Wenjing Liu Committed by Alex Deucher
Browse files

drm/amd/display: do not reset lane count in EQ fallback 



[Description]
According to DP1.4 specs we should not reset lane count back
when falling back in failing EQ training.
This causes PHY test pattern compliance to fail as infinite LT
when LT fails EQ to 4 RBR and fails CR in a loop.

Signed-off-by: default avatarWenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 15659045

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+0 −2
Original line number Diff line number Diff line
@@ -1302,8 +1302,6 @@ bool decide_fallback_link_setting( 
					current_link_setting->lane_count);

		} else if (!reached_minimum_link_rate

				(current_link_setting->link_rate)) {

			current_link_setting->lane_count =

				initial_link_settings.lane_count;

			current_link_setting->link_rate =

				reduce_link_rate(

					current_link_setting->link_rate);